$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Forming a diffusion break during a RMG process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/76
  • H01L-029/78
  • H01L-021/762
  • H01L-021/02
출원번호 US-0921377 (2013-06-19)
등록번호 US-8846491 (2014-09-30)
발명자 / 주소
  • Pham, Daniel
  • Hu, Zhenyu
  • Wei, Andy
  • LiCausi, Nicholas V.
출원인 / 주소
  • GLOBALFOUNDRIES Inc.
대리인 / 주소
    Pogue, Darrell L.
인용정보 피인용 횟수 : 29  인용 특허 : 1

초록

Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial j

대표청구항

1. A method for forming a device, the method comprising: providing a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate;providing a dielectric material over an epitaxial junction area;forming an opening between the set of RMG structures and through the set o

이 특허에 인용된 특허 (1)

  1. Banna, Srinvasa; Wei, Andy C., Replacement metal gate diffusion break formation.

이 특허를 인용한 특허 (29)

  1. Reznicek, Alexander; Kanakasabapathy, Sivananda, Double diffusion break gate structure without vestigial antenna capacitance.
  2. Reznicek, Alexander; Kanakasabapathy, Sivananda, Double diffusion break gate structure without vestigial antenna capacitance.
  3. Choi, Youn Sung; Roh, Ukjin; Ekbote, Shashank, Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout.
  4. Choi, Youn Sung; Roh, Ukjin; Ekbote, Shashank, Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout.
  5. Jagannathan, Hemanth; Kanakasabapathy, Sivananda K.; Paruchuri, Vamsi K.; Reznicek, Alexander, Fin cut enabling single diffusion breaks.
  6. Basker, Veeraraghavan S.; Cheng, Kangguo; Standaert, Theodorus E.; Wang, Junli, Fin field-effect transistor (FinFET) with reduced parasitic capacitance.
  7. Basker, Veeraraghavan S.; Cheng, Kangguo; Standaert, Theodorus E.; Wang, Junli, Fin field-effect transistor (FinFET) with reduced parasitic capacitance.
  8. Dou, Xinyuan; Yu, Hong; Gu, Sipeng; Wang, Yanzhen, Fin-type field effect transistors with single-diffusion breaks and method.
  9. Wang, Haiting; Zhao, Wei; Yu, Hong; Wu, Xusheng; Zang, Hui; Hu, Zhenyu, Fin-type field effect transistors with single-diffusion breaks and method.
  10. Wang, Haiting; Zhao, Wei; Yu, Hong; Wu, Xusheng; Zang, Hui; Hu, Zhenyu, Fin-type field effect transistors with single-diffusion breaks and method.
  11. Economikos, Laertis; Park, Chanro; Xie, Ruilong; Liu, Pei, Forming of marking trenches in structure for multiple patterning lithography.
  12. Cheng, Kangguo; Greene, Andrew M.; Sporre, John R.; Xu, Peng, Gate cut device fabrication with extended height gates.
  13. Yu, Hong; Dou, Xinyuan; Zhan, Hui; Hu, Zhenyu, Integrated circuit structure including single diffusion break and end isolation region, and methods of forming same.
  14. Chang, Che-Cheng; Lin, Chih-Han; Lin, Jr-Jung, Method and structure for FinFet isolation.
  15. Zhao, Wei; Wang, Haiting; Shen, Hongliang; Hu, Zhenyu; Chi, Min-Hwa, Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices.
  16. Wu, Xusheng; Xiao, Changyong; He, Wanxun; Shen, Hongliang, Product comprised of FinFET devices with single diffusion break isolation structures.
  17. Wu, Xusheng; Xiao, Changyong; He, Wanxun; Shen, Hongliang, Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product.
  18. Cheng, Kangguo; Xu, Peng, Self-aligned gate cut with polysilicon liner oxidation.
  19. Liou, En-Chiuan; Yang, Chih-Wei; Tung, Yu-Cheng; Tseng, Chia-Hsun, Semiconductive device with a single diffusion break and method of fabricating the same.
  20. Kim, Ju-Youn; Kim, Min-Choul; Sung, Baik-Min; Woo, Sang-Hyun, Semiconductor device.
  21. Kim, Dong-Kwon; Seo, Kang-Ill, Semiconductor device and method for fabricating the same.
  22. Kwon, Byoung-Ho; Kim, Cheol; Kim, Ho-Young; Park, Se-Jung; Kim, Myeong-Cheol; Kang, Bo-Kyeong; Yoon, Bo-Un; Choi, Jae-Kwang; Choi, Si-Young; Jeong, Suk-Hoon; Seong, Geum-Jung; Jeong, Hee-Don; Choi, Yong-Joon; Han, Ji-Eun, Semiconductor device and method for fabricating the same.
  23. Liou, En-Chiuan; Yang, Chih-Wei; Tung, Yu-Cheng; Wu, Chun-Yuan, Semiconductor device and method for fabricating the same.
  24. Kim, Ju-Youn; Kim, Min-Choul; Sung, Baik-Min; Woo, Sang-Hyun, Semiconductor device having a device isolation layer.
  25. Yeo, Kyoung Hwan; Bai, KeunHee; Ha, Seungseok; Park, Eunsil; Paak, Sunhom Steve; Shin, Heonjong; Cha, Dongho, Semiconductor devices and methods of manufacturing the same.
  26. Zang, Hui; Chi, Min-hwa, Semiconductor fin loop for use with diffusion break.
  27. Hsu, Meng-Fang; Wu, Pei-Lin; Liang, Chun-Sheng, Semiconductor structure and manufacturing method thereof.
  28. Zang, Hui; Liu, Bingwu, Single diffusion break with improved isolation and process window and reduced cost.
  29. Wang, Yanzhen; Zang, Hui; Liu, Bingwu, Single-diffusion break structure for fin-type field effect transistors.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로