A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response da
A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.
대표청구항▼
1. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to: responsive to a second processor identifying that a flag has been
1. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to: responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, copy, by the second processor, an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor;delete, by the second processor, the I/O response from the first I/O response data structure;clear, by the second processor, the flag;process, by the second processor, the I/O operation by addressing the I/O response in the second I/O response data structure; andresponsive to completing the I/O operation, delete, by the second processor, the I/O response from the second I/O response data structure. 2. The computer program product of claim 1, wherein the flag is in a flag data structure in a shared memory area. 3. The computer program product of claim 1, wherein the first I/O response data structure is in a private memory area owned by the first processor. 4. The computer program product of claim 1, wherein the second I/O response data structure is in a private memory area owned by the second processor. 5. The computer program product of claim 1, wherein the computer readable program causes the second processor to gain access to the first I/O response data structure by causing the computing device to: lock, by the second processor, the first I/O response data structure prior to copying the I/O response from the first I/O response data structure associated with the first processor to the second I/O response data structure associated with the second processor; andresponsive to the second processor deleting the I/O response from the first I/O response data structure, unlock, by the second processor, the first I/O response data structure. 6. The computer program product of claim 5, wherein the computer readable program further causes the computing device to: prior to the second processor locking the first I/O response data structure, determine, by the second processor, whether another processor has already obtained a lock on the first I/O response data structure;responsive to a determination, by the second processor, that no other processor has obtained the lock on the first I/O response data structure, proceed, by the second processor, with obtaining the lock on the first I/O response data structure; andresponsive to a determination, by the second processor, that the other processor has obtained the lock on the first I/O response data structure, discontinue, by the second processor, the process of assisting in completion of the I/O operation. 7. The computer program product of claim 1, wherein the computer readable program further causes the computing device to: responsive to the first processor completing higher priority work and identifying that the flag was set by a first processor requesting assistance in completing the I/O operation, clear, by the first processor, the flag;process, by the first processor, the I/O operation by addressing the I/O response in the second I/O response data structure; andresponsive to completing the I/O operation, delete, by the first processor, the I/O espouse from the first I/O response data structure. 8. The computer program product of claim 1, wherein the flag indicating the requested assistance in completing the I/O operation is set by the computer readable program further causing the computing device to: responsive to the I/O response being migratable, access, by the first processor, a timestamp associated with the I/O response entry in the first I/O response data structure;subtract, by the first processor, the time value associated with the timestamp from a current time, thereby forming a wait time;determine, by the first processor, whether the wait time exceeds a wait-time threshold value; andresponsive to the wait time exceeding the wait-time threshold value, set, by the first processor, the flag in a flag data structure in a shared memory area. 9. An apparatus, comprising: a first processor;a second processor; anda memory coupled to the first processor and the second processor, wherein the memory comprises instructions which, when executed, cause the second processor to:responsive to the second processor identifying that a flag has been set by the first processor requesting assistance in completing an I/O operation, copy an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor;delete the I/O response from the first I/O response data structure;clear the flag;process the I/O operation by addressing the I/O response in the second I/O response data structure; andresponsive to completing the I/O operation, delete the I/O response from the second I/O response data structure. 10. The apparatus of claim 9, wherein the flag is in a flag data structure in a shared memory area. 11. The apparatus of claim 9, wherein the first I/O response data structure is in a private memory area owned by the first processor. 12. The apparatus of claim 9, wherein the second I/O response data structure is in a private memory area owned by the second processor. 13. The apparatus of claim 9, wherein the instructions cause the second processor to gain access to the first I/O response data structure by causing the second processor to: lock the first I/O response data structure prior to copying the I/O response from the first I/O response data structure associated with the first processor to the second I/O response data structure associated with the second processor; andresponsive to the second processor deleting the I/O response from the first I/O response data structure, unlock the first I/O response data structure. 14. The apparatus of claim 13, wherein the instructions further cause the second processor to: prior to the second processor locking the first I/O response data structure, determine whether another processor has already obtained a lock on the first I/O response data structure;responsive to a determination, by the second processor, that no other processor has obtained the lock on the first I/O response data structure, proceed with obtaining the lock on the first I/O response data structure; andresponsive to a determination, by the second processor, that the other processor has obtained the lock on the first I/O response data structure, discontinue the process of assisting in completion of the I/O operation. 15. The apparatus of claim 9, wherein the instructions further cause the first processor to: responsive to the first processor completing higher priority work and identifying that the flag was set by a first processor requesting assistance in completing the I/O operation, clear the flag;process the I/O operation by addressing the I/O response in the second I/O response data structure; andresponsive to completing the I/O operation, delete the I/O response from the first I/O response data structure. 16. The apparatus of claim 9, wherein the flag indicating the requested assistance in completing the I/O operation is set by the instructions further causing the first processor to: responsive to the I/O response being migratable, access a timestamp associated with the I/O response entry in the first I/O response data structure;subtract the time value associated with the timestamp from a current time, thereby forming a wait time;determine whether the wait time exceeds a wait-time threshold value; andresponsive to the wait time exceeding the wait-time threshold value, set the flag in a flag data structure in a shared memory area.
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이 특허에 인용된 특허 (3)
Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
Nordstrom Gregory Michael ; Lambeth Shawn Michael ; Movall Paul Edward ; Moertl Daniel Frank ; Graham Charles Scott ; Armstrong William Joseph ; Sand Thomas Rembert, Interrupt and message batching apparatus and method.
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