초록 ▼

Provided is a thin film transistor including a gate electrode on a substrate; a gate insulating layer on the gate electrode; source and drain electrodes including first source and drain layers on the gate insulating layer, respectively, and spaced apart from each other, wherein at lease one of the f

Provided is a thin film transistor including a gate electrode on a substrate; a gate insulating layer on the gate electrode; source and drain electrodes including first source and drain layers on the gate insulating layer, respectively, and spaced apart from each other, wherein at lease one of the first source and drain layers includes indium-tin-oxide doped with at least one Group III element; and an organic semiconductor layer on the gate insulating layer and contacting the first source and drain layers.

대표청구항 ▼

1. A method of fabricating a thin film transistor, comprising: forming a gate electrode on a substrate;depositing a gate insulating layer on the gate electrode and the substrate at a temperature of equal to or less than 200° C.;forming source and drain electrodes on the gate insulating layer spaced

1. A method of fabricating a thin film transistor, comprising: forming a gate electrode on a substrate;depositing a gate insulating layer on the gate electrode and the substrate at a temperature of equal to or less than 200° C.;forming source and drain electrodes on the gate insulating layer spaced apart from each other by depositing indium-tin-oxide (ITO) on the gate insulating layer at a temperature less than 200° C., the source and drain electrodes including source and drain layers formed of the ITO doped with at least one Group III element;forming smooth surfaces of the source and drain layers by heat-treating the source and drain electrodes at a temperature of less than 200° C.; andafter the step of forming the smooth surfaces of the source and drain layers, forming an organic semiconductor layer on the gate insulating layer to contact the source and drain layers that are formed of the ITO doped with at least one Group III element and have the smooth surfaces,wherein an upper surface of the gate insulating layer is even so that the source and drain electrodes do not have steps in a cross section but are smooth and even,wherein the forming of the organic semiconductor layer includes evaporating the organic semiconductor layer at a temperature of less than 200° C. and depositing the evaporated organic semiconductor material on the substrate having the source and drain electrodes by using a shadow mask, andwherein the heat treating of the source and drain electrodes is performed to recover and smooth at least one roughened doped ITO surface of the source and drain electrodes from the depositing of the ITO. 2. The method according to claim 1, wherein the Group III element is boron. 3. The method according to claim 1, wherein the indium-tin-oxide is doped with the at least one Group III element in a dose range of about 1*1014 to 9*1014 ions/cm2. 4. The method according to claim 1, wherein the organic semiconductor layer comprises at least one of pentacene, an arylamine, a thiophene, tetracene, a naphthalene and anthracene. 5. The method according to claim 1, wherein the organic semiconductor layer substantially fills the space between the source and drain electrodes and overlaps at least a part of the source and drain electrodes. 6. The method according to claim 1, wherein the gate insulating layer comprises at least one of benzocyclobutene (BCB) and polyvinylpyrrolidone (PVP).