초록 ▼

This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes

This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.

대표청구항 ▼

1. A circuit comprising: a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal;a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibit

1. A circuit comprising: a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal;a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibiting hysteresis with a lower threshold and an upper threshold; andan output block configured to receive the first output signal and the second output signal and to generate a third output signal based on the first and second output signals, the output block being configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal, wherein the first buffer exhibits hysteresis with a lower threshold and an upper threshold, and the upper threshold of the second buffer is more positive than the upper threshold of the first buffer, and wherein the lower threshold of the second buffer is more negative than the lower threshold of the first buffer. 2. The circuit of claim 1, wherein, from an initial state in which the incoming signal is low, the first output signal is in a first logic state, the second output signal is in a second logic state, and the third output signal is in a third logic state: when the incoming signal rises above the upper threshold of the first buffer, the first buffer transitions the first output signal to a fourth logic state, the output block transitions the third output signal to a sixth logic state based on the fourth logic state, and the output block locks the third output signal in the sixth logic state based on the fourth logic state; andwhen the incoming signal rises above the upper threshold of the second buffer, the second buffer transitions the second output signal to a fifth logic state, and the output block unlocks the third output signal based on the fifth logic state. 3. The circuit of claim 2, wherein: when the incoming signal falls below the lower threshold of the first buffer, the first buffer transitions the first output signal to the first logic state, the output block transitions the third output signal to the third logic state based on the first logic state, and the output block locks the third output signal in the third logic state based on the first logic state; andwhen the incoming signal falls below the lower threshold of the second buffer, the second buffer transitions the second output signal to the second logic state, and the output block unlocks the third output signal based on the second logic state. 4. The circuit of claim 1, wherein the first buffer has substantially zero hysteresis and wherein the lower threshold and the upper threshold of the first buffer are both approximately at a first threshold. 5. The circuit of claim 4, wherein, from an initial state in which the incoming signal is low, the first output signal is in a first logic state, the second output signal is in a second logic state, and the third output signal is in a third logic state: when the incoming signal rises above the first threshold, the first buffer transitions the first output signal to a fourth logic state, the output block transitions the third output signal to a sixth logic state based on the fourth logic state, and the output block locks the third output signal in the sixth logic state based on the fourth logic state; andwhen the incoming signal rises above the upper threshold of the second buffer, the second buffer transitions the second output signal to a fifth logic state, and the output block unlocks the third output signal based on the fifth logic state. 6. The circuit of claim 5, wherein: when the incoming signal falls below the first threshold, the first buffer transitions the first output signal to the first logic state, the output block transitions the third output signal to the third logic state based on the first logic state, and the output block locks the third output signal in the third logic state based on the first logic state; andwhen the incoming signal falls below the lower threshold of the second buffer, the second buffer transitions the second output signal to the second logic state, and the output block unlocks the third output signal based on the second logic state. 7. The circuit of claim 1, wherein one or both of the first buffer and the second buffer is or includes a Schmitt trigger circuit. 8. The circuit of claim 1, wherein the output block is configured to lock and unlock the third output signal by latching and unlatching, respectively, the third output signal in response to transitions of the second buffer. 9. A circuit comprising: a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal, the first buffer having one or more first thresholds;a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibiting hysteresis with a lower threshold and an upper threshold; andan output block configured to receive the first output signal and the second output signal and to generate a third output signal based on the first and second output signals, the output block being configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal;wherein, from an initial state in which the incoming signal is low, the first output signal is in a first logic state, the second output signal is in a second logic state, and the third output signal is in a third logic state: when the incoming signal rises above the one or more first thresholds, the first buffer transitions the first output signal to a fourth logic state, the output block transitions the third output signal to a sixth logic state based on the fourth logic state, and the output block locks the third output signal in the sixth logic state based on the fourth logic state; andwhen the incoming signal rises above the upper threshold of the second buffer, the second buffer transitions the second output signal to a fifth logic state, and the output block unlocks the third output signal based on the fifth logic state.wherein, from an initial state in which the incoming signal is high, the first output signal is in the fourth logic state, the second output signal is in the fifth logic state, and the third output signal is in the sixth logic state: when the incoming signal falls below the one or more first thresholds, the first buffer transitions the first output signal to the first logic state, the output block transitions the third output signal to the third logic state based on the first logic state, and the output block locks the third output signal in the third logic state based on the first logic state; andwhen the incoming signal falls below the lower threshold of the second buffer, the second buffer transitions the second output signal to the second logic state, and the output block unlocks the third output signal based on the second logic state. 10. The circuit of claim 9, wherein the first buffer exhibits hysteresis with a lower threshold and an upper threshold, and wherein the one or more first thresholds consist of the lower threshold of the first buffer and the upper threshold of the first buffer. 11. The circuit of claim 10, wherein the upper threshold of the second buffer is more positive than the upper threshold of the first buffer, and wherein the lower threshold of the second buffer is more negative than the lower threshold of the first buffer. 12. The circuit of claim 9, wherein the first buffer has substantially zero hysteresis and wherein the one or more first thresholds consist of a single first threshold. 13. The circuit of claim 9, wherein one or both of the first buffer and the second buffer is or includes a Schmitt trigger circuit. 14. A memory device comprising: a first buffer configured to receive an incoming signal and to generate a first output signal based on the incoming signal, the first buffer having one or more first thresholds;a second buffer configured to receive the incoming signal and to generate a second output signal based on the incoming signal, the second buffer exhibiting hysteresis with a lower threshold and an upper threshold; andan output block configured to receive the first output signal and the second output signal and to generate a third output signal based on the first and second output signals, the output block being configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal;wherein, from an initial state in which the incoming signal is low, the first output signal is in a first logic state, the second output signal is in a second logic state, and the third output signal is in a third logic state: when the incoming signal rises above the one or more first thresholds, the first buffer transitions the first output signal to a fourth logic state, the output block transitions the third output signal to a sixth logic state based on the fourth logic state, and the output block locks the third output signal in the sixth logic state based on the fourth logic state; andwhen the incoming signal rises above the upper threshold of the second buffer, the second buffer transitions the second output signal to a fifth logic state, and the output block unlocks the third output signal based on the fifth logic state.wherein, from an initial state in which the incoming signal is high, the first output signal is in the fourth logic state, the second output signal is in the fifth logic state, and the third output signal is in the sixth logic state: when the incoming signal falls below the one or more first thresholds, the first buffer transitions the first output signal to the first logic state, the output block transitions the third output signal to the third logic state based on the first logic state, and the output block locks the third output signal in the third logic state based on the first logic state; andwhen the incoming signal falls below the lower threshold of the second buffer, the second buffer transitions the second output signal to the second logic state, and the output block unlocks the third output signal based on the second logic state. 15. The memory device of claim 14, wherein the first buffer has substantially zero hysteresis. 16. The memory device of claim 14, wherein one or both of the first buffer and the second buffer is or includes a Schmitt trigger circuit. 17. The memory device of claim 14, wherein the incoming signal is a data signal. 18. The memory device of claim 14, wherein the incoming signal is a clock signal.