초록 ▼

A master stage (502) of a master-slave flip-flop (500) includes an input terminal (504) for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals, a transmission gate (522) coupled to the input terminal and having an output terminal, a storage element (520

A master stage (502) of a master-slave flip-flop (500) includes an input terminal (504) for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals, a transmission gate (522) coupled to the input terminal and having an output terminal, a storage element (520) coupled to the output terminal of the transmission gate, and a two-input logic gate (525) having a first input terminal (541) coupled to the storage element, a parallel input terminal (542) coupled to the input terminal of the master stage, and an output terminal (543) that provides an output terminal of the master stage. A slave stage (503) has terminals for receiving second clock signals, wherein first clock signals are delayed relative to second clock signals.

대표청구항 ▼

1. A parallel master-slave flip-flop (“PMSFF”) having an input terminal for receiving a data-in signal and an output terminal for outputting a data-out signal, comprising: a master stage comprising an input terminal for receiving the data-in signal, an output terminal, and terminals for receiving fi

1. A parallel master-slave flip-flop (“PMSFF”) having an input terminal for receiving a data-in signal and an output terminal for outputting a data-out signal, comprising: a master stage comprising an input terminal for receiving the data-in signal, an output terminal, and terminals for receiving first clock signals (MCLK and MCLKB), the master stage configured to latch data at the master stage and to output the data latched at the master stage based on the first clock signals, wherein the master stage includes: a transmission gate coupled to the input terminal of the master stage, the transmission gate having a control terminal to receive MCLK, another control terminal to receive MCLKB, and an output terminal,a storage element coupled to the output terminal of the transmission gate, wherein the storage element either latches the data-in signal or is transparent, depending on MCLK and MCLKB, anda two-input logic gate having a first input terminal coupled to the storage element, a parallel input terminal coupled to the input terminal of the master stage, and an output terminal that provides an output terminal of the master stage; anda slave stage comprising an input terminal coupled to the output terminal of the master stage, an output terminal for outputting the data-out signal, and terminals for receiving second clock signals (CLK and CLKB), the slave stage configured to latch data at the slave stage and to output the data latched at the slave stage based on the second clock signals. 2. The PMSFF of claim 1, wherein the first clock signals are delayed relative to corresponding second clock signals by a delay element by an amount of time tdelay. 3. The PMSFF of claim 1, wherein the data-in signal is in a stable high state, when the master stage of the PMSFF is non-transparent. 4. The PMSFF of claim 3, wherein the two-input logic gate is a NAND gate. 5. The PMSFF of claim 1, wherein the data-in signal is in a stable low state, when the master stage of the PMSFF is non-transparent. 6. The PMSFF of claim 5, wherein the two-input logic gate is a NOR gate. 7. The PMSFF of claim 1, wherein the storage element includes an inverter having an input terminal coupled to the transmission gate, and an output terminal, anda tri-state inverter having an input terminal coupled to the output terminal of the inverter, an output terminal coupled to the input terminal of the inverter, a control input for receiving MCLK and another control terminal for receiving MCLKB. 8. The PMSFF of claim 7, wherein the first clock signals are delayed relative to corresponding second clock signals by an amount of time tdelay where tdelay is substantially equal to a propagation delay through the transmission gate plus a propagation delay through the inverter of the storage element of the master stage. 9. The PMSFF of claim 1, further comprising: a test control stage including:an input terminal coupled to the input terminal of the PMSFF,a test-input terminal for receiving a test-input signal, wherein the test-input terminal of the test control stage provides a test-input terminal of the PMSFF,terminals for receiving test-enable signals (TE and TEB), andan output terminal coupled to the input terminal of the master stage,wherein the master stage receives one of the data-in signal and the test-input signal, based on values of the test enable signals. 10. The PMSFF of claim 9, wherein the test control stage further includes: a first tri-state inverter having an input terminal coupled to the input terminal of the test control stage, a control terminal for receiving TE, another control terminal for receiving TEB, and an output terminal,a second tri-state inverter having an input coupled to the test-input terminal of the test control stage, a control terminal for receiving TE, another control terminal for receiving TEB, and an output terminal, andwherein the output terminals of the tri-state inverters are coupled to a common node that is coupled to the output terminal of the test control stage. 11. The PMSFF of claim 10, wherein the first clock signals are delayed relative to corresponding second clock signals by an amount of time tdelay where tdelay is substantially equal to a sum of a propagation delay through the first tri-state inverter of the test control stage, a propagation delay through the transmission gate and a propagation delay through the inverter of the storage element of the master stage. 12. The PMSFF of claim 10, including a delay element coupled between the test-input terminal of the PMSFF and the input terminal of the test control stage, wherein the delay element delays the test-input signal by the amount of time tdelay. 13. The PMSFF of claim 10, including additional circuitry for changing behavior of MCLK based on a value of TE, the additional circuitry including: a delay element having an input terminal for receiving CLK and an output terminal, the delay element delaying CLK by the amount of time tdelay,a first tri-state inverter having an input terminal coupled to the output terminal of the delay element, a control terminal for receiving TE, another control terminal for receiving TEB, and an output terminal, anda second tri-state inverter having an input coupled to the output terminal of the delay element, a control terminal for receiving TE, another control terminal for receiving TEB, and an output terminal,wherein the output terminals of the tri-state inverters are coupled to a common node that provides MCLK to the PMSFF, andwherein MCLK is delayed by the amount of time tdelay when the PMSFF is in a normal mode, and MCLK is not delayed when the PMSFF is in a test mode. 14. A circuit, comprising: a dynamic circuit module having at least one output terminal for outputting dynamic digital data based on a clock signal (CLK); anda parallel master-slave flip-flop (“PMSFF”) having an input terminal for receiving the dynamic digital data and an output terminal for outputting a data-out signal, the PMSFF further comprising: a master stage comprising an input terminal for receiving the dynamic digital data, an output terminal, and terminals for receiving first clock signals (MCLK and MCLKB), the master stage configured to latch data at the master stage and to output the data latched at the master stage based on the first clock signals, wherein the master stage includes: a transmission gate, coupled to the input terminal of the master stage, having a control terminal to receive MCLK, another control terminal to receive MCLKB, and an output terminal,a storage element coupled to the output terminal of the transmission gate, anda NAND gate having a first input terminal coupled to the storage element, a parallel input terminal coupled to the input terminal of the master stage, and an output terminal that provides an output terminal of the master stage; anda slave stage comprising an input terminal coupled to the output terminal of the master stage, an output terminal for outputting the data-out signal, and terminals for receiving second clock signals (CLK and CLKB), the slave stage configured to latch data at the slave stage and to output the data latched at the slave stage based on the second clock signals. 15. The circuit of claim 14, wherein MCLK is delayed relative to CLK by an amount of time tdelay, and MCLKB is delayed relative to CLKB by the amount of time tdelay. 16. The circuit of claim 14, wherein the dynamic digital data is in a stable high state, when the master stage of the PMSFF is non-transparent. 17. The circuit of claim 14, wherein the dynamic circuit module includes at least one improved sense amplifier having an output terminal for providing the at least one output terminal of the dynamic circuit module. 18. The circuit of claim 17, wherein the dynamic circuit module includes a static random access memory coupled to the sense amplifier. 19. A memory system, comprising: a static random access memory including a bitcell, the bitcell having terminals for outputting an intermediate differential voltage when the bitcell is accessed, the bitcell having a differential development time for developing the intermediate differential voltage;an improved sense amplifier for receiving the intermediate differential voltage and for outputting a differential voltage; anda parallel master-slave flip-flop (“PMSFF”) having an input terminal for receiving the differential voltage and an output terminal for outputting a data-out signal, the PMSFF including:a master stage comprising an input terminal for receiving the differential voltage, an output terminal, and terminals for receiving first clock signals (MCLK and MCLKB), the master stage configured to latch data at the master stage and to output the data latched at the master stage based on the first clock signals, the master stage having a setup time, wherein the master stage includes: a transmission gate, coupled to the input terminal of the master stage, having a control terminal to receive MCLK, another control terminal to receive MCLKB, and an output terminal,a storage element coupled to the output terminal of the transmission gate, wherein the storage element either latches the differential voltage or is transparent, depending on MCLK and MCLKB, anda two-input logic gate having a first input terminal coupled to the storage element, a parallel input terminal coupled to the input terminal of the master stage, and an output terminal that provides an output terminal of the master stage; anda slave stage comprising an input terminal coupled to the output terminal of the master stage, an output terminal for outputting the data-out signal, and terminals for receiving second clock signals (CLK and CLKB), the slave stage configured to latch data at the slave stage and to output the data latched at the slave stage based on the second clock signals. 20. The memory system of claim 19, wherein an increase in the differential development time of the bitcell is proportional to a decrease in the setup time of the master stage of the PMSFF.