Conductive path in switching material in a resistive random access memory device and control
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/08
H01L-029/417
H01L-029/49
H01L-045/00
출원번호
US-0870919
(2013-04-25)
등록번호
US-8912523
(2014-12-16)
발명자
/ 주소
Jo, Sung Hyun
출원인 / 주소
Crossbar, Inc.
대리인 / 주소
Ogawa P.C.
인용정보
피인용 횟수 :
0인용 특허 :
127
초록▼
A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm dis
A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.
대표청구항▼
1. A device including a non-volatile memory device comprising: a first electrode disposed upon a semiconductor substrate;a second electrode comprising a metal material;a resistive switching material layer comprising an amorphous silicon material overlying the first electrode;a dielectric material la
1. A device including a non-volatile memory device comprising: a first electrode disposed upon a semiconductor substrate;a second electrode comprising a metal material;a resistive switching material layer comprising an amorphous silicon material overlying the first electrode;a dielectric material layer disposed between the second electrode and the resistive switching material layer, the dielectric material layer being sufficiently thin to electrically breakdown in a region when a first voltage is applied to the second electrode and to cause formation of an electrical breakdown open region in a portion of the dielectric material layer, the electrical breakdown open region having a first dimension to allow a first metal region to form within the portion of the dielectric material layer and extending in a portion of the resistive switching material layer from the metal material; anda buffer material layer comprising a p+polycrystalline silicon-containing material disposed between the first electrode and the resistive switching material layer to control an interfacial defect level between the first electrode and the resistive switching material layer; andwherein the non-volatile memory device includes at least the buffer material layer, the dielectric material layer, the resistive switching material layer and a portion of the second electrode. 2. A method of forming a non-volatile memory device, comprising: providing a semiconductor substrate having a surface region,forming a first dielectric material overlying the surface region of the semiconductor substrate;forming a first electrode structure overlying the dielectric material;forming a buffer material comprising a p+polycrystalline silicon-containing material interposed between the first electrode and the amorphous silicon material to control an interfacial defect level between the first electrode and the amorphous silicon material;forming a resistive switching material comprising an amorphous silicon material overlying the first electrode and the p+ polycrystalline silicon-containing material;forming a second electrode comprising a metal material overlying the resistive switching material; andforming a thickness of second dielectric material disposed between the second electrode and the resistive switching layer, the thickness of second dielectric material being configured to electrically breakdown in a localized region by applying a first voltage to the second electrode to form an open region in a portion of the thickness of second dielectric material, the opening region having a first dimension to cause a first metal region to form in the portion of the thickness of the second dielectric material and in a portion of the resistive switching material from the metal material upon applying of the first voltage. 3. The method of claim 2 wherein the semiconductor substrate comprises a single crystal silicon, a silicon germanium material, or a silicon on insulator (SOI) substrate. 4. The method of claim 2 wherein the semiconductor substrate comprises one or more transistor devices for controlling circuitry for the device. 5. The method of claim 2 wherein the first dielectric material comprises a silicon oxide, a silicon nitride, a low K dielectric, a high K dielectric, or a silicon oxide on silicon nitride on silicon oxide stack. 6. The method of claim 2 wherein the first electrode structure comprises tungsten, copper, aluminum, or a doped semiconductor material. 7. The method of claim 2 wherein the metal material is selected from a group consisting of: silver, platinum, palladium, nickel, aluminum. 8. The method of claim 2 wherein the thickness of second dielectric material is selected from a group consisting of: silicon dioxide, silicon nitride, hafnium oxide, aerogel, and aluminum oxide. 9. The method of claim 2 wherein the first voltage is an electroforming voltage. 10. The method of claim 2 the metal material is selected from a group consisting of: silver, platinum, palladium, nickel, and aluminum. 11. The method of claim 2 wherein the second electrode further comprises a portion for a wiring material selected from a group consisting of: tungsten, copper, and aluminum. 12. The method of claim 2 wherein the thickness of second dielectric material has a non-zero thickness of about 5 nm or less. 13. A device including non-volatile memory device comprising: a seminconductor substrate including a plurality of transistors;a first electrode disposed upon the semiconductor substrate;a buffer material layer disposed upon the first electrode, wherein the buffer material layer comprises a doped polycrystalline silicon bearing material, wherein the buffer material layer controls an interfacial defect level between the first electrode and the resistive switching material layer;a resistive switching material layer disposed upon the buffer material layer, wherein the resistive switching material layer comprises an amorphous silicon material;a second electrode disposed above the resistive switching material layer comprising a metal material; anda dielectric material layer disposed between the second electrode and upon the resistive switching layer, wherein the dielectric material layer being sufficiently thin to electrically breakdown in a region when a first voltage is applied to the second electrode and to cause formation of an electric breakdown open region in a portion of the dielectric material layer, the electric breakdown open region having a first dimension to allow a first metal region to form within the portion of the dielectric material layer and to extend in a portion of the resistive switching material layer from the metal material, wherein the dielectric material layer has a non-zero thickness of less than approximately 5 nm; and. 14. The device of claim 13 wherein the metal material is selected from a group consisting of: silver material, platinum, palladium, nickel, and aluminum. 15. The device of claim 1 wherein the semiconductor substrate includes one or more transistor devices for controlling circuitry configured to control the non-volatile memory device. 16. The device of claim 1 wherein the metal material is configured to diffuse within the resistive switching material layer. 17. The device of claim 1 wherein the metal material is selected from a group consisting of: silver, platinum, palladium, nickel, aluminum. 18. The device of claim 1 wherein the dielectric material layer is selected from a group consisting of: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide. 19. The device of claim 1 wherein the dielectric material layer has a non-zero thickness of about 5 nm or less.
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