Video decoding system having a programmable variable-length decoder
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04N-007/18
H04N-019/12
H04N-019/82
G06F-009/38
H04N-019/70
H04N-005/445
G09G-005/14
H04N-019/423
H04N-019/129
H04N-019/157
H04N-009/64
H04N-019/60
H04N-019/91
G09G-005/36
H04N-019/44
H04N-019/90
H04N-019/122
H04N-019/176
H04N-019/61
G09G-005/06
G09G-005/28
G09G-005/34
G09G-005/12
출원번호
US-0404387
(2003-04-01)
등록번호
US-8913667
(2014-12-16)
발명자
/ 주소
Hsiun, Vivian
MacInnis, Alexander G.
Xie, Xiaodong
출원인 / 주소
Broadcom Corporation
대리인 / 주소
Foley & Lardner LLP
인용정보
피인용 횟수 :
0인용 특허 :
180
초록▼
Video decoding system having a programmable variable-length decoding accelerator. The system includes a decoder processor and a variable-length decoding accelerator. The variable-length decoding accelerator is coupled to the decoder processor and performs variable-length decoding operations on varia
Video decoding system having a programmable variable-length decoding accelerator. The system includes a decoder processor and a variable-length decoding accelerator. The variable-length decoding accelerator is coupled to the decoder processor and performs variable-length decoding operations on variable-length code in the video data stream. The variable-length decoding accelerator is capable of decoding variable-length code according to any of a plurality of decoding methods. In one embodiment, the variable-length decoder includes a plurality of code tables stored in memory and a code table selection register that is programmable to dictate which of the plurality of code tables is to be utilized to decode variable-length code. In one embodiment, the decoding system includes two variable-length decoding accelerators.
대표청구항▼
1. A video decoding system comprising: a decoder processor configured to perform decoding functions on a video data stream;a first variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on macroblock data elements in the vi
1. A video decoding system comprising: a decoder processor configured to perform decoding functions on a video data stream;a first variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on macroblock data elements in the video data stream, each macroblock data element representing a macroblock of a video frame, each macroblock data element comprising a macroblock header and coefficient data;a second variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on macroblock data elements in the video data stream; andwherein the first and second variable-length decoding accelerators are configured to alternately decode macroblock data elements in the video data stream such that the first variable-length decoding accelerator decodes a macroblock header of one macroblock data element while the second variable-length decoding accelerator decodes coefficient data of another macroblock data element during a first stage of decoding, and the second variable-length decoding accelerator decodes a macroblock header of one macroblock data element while the first variable-length decoding accelerator decodes coefficient data of another macroblock data element during a second stage of decoding. 2. The system of claim 1, wherein each of the variable-length decoding accelerators is configured to decode the macroblock header of each macroblock data element before decoding the coefficient data of the macroblock data element. 3. The system of claim 1, wherein the variable-length decoding accelerators are configured such that the decoding of successive macroblock data elements in the data stream is initiated during corresponding successive variable time periods. 4. The system of claim 3, wherein the variable-length decoding accelerators are configured such that the decoding of each macroblock data element in the data stream is completed before an end of the variable time period that follows the variable time period in which decoding of that macroblock data element was initiated. 5. A video decoding system comprising: a decoder processor configured to perform decoding functions on a video data stream;a first variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on variable-length code in the video data stream, wherein the first variable-length decoding accelerator is configured by the decoder processor to decode variable-length codes according to any of a plurality of different decoding formats selected by the decoder processor based at least in part on a coding format of the variable video data stream, wherein the first variable-length decoding accelerator is configured to use for the selected decoding format a variable-length coding table of a plurality of different variable-length coding tables stored in memory that respectively correspond to the plurality of different decoding formats; anda second variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on variable-length code in the video data stream. 6. The system of claim 5, wherein each of the plurality of different variable-length coding tables matches variable-length codes to their corresponding decoded information. 7. The system of claim 5, wherein the first variable-length decoding accelerator further comprises a register that dictates which of the plurality of different variable-length coding tables is to be utilized to decode a variable-length code, wherein the register is programmable to dictate the appropriate different variable-length coding table to be employed. 8. The system of claim 5, wherein the second variable-length decoding accelerator is hard-wired to decode a variable-length code according to a particular decoding method. 9. The system of claim 5, wherein the second variable-length decoding accelerator is configured to decode a variable-length code according to any of the plurality of different decoding formats. 10. A video decoding system comprising: a decoder processor configured to perform decoding functions on a video data stream;a variable-length decoding accelerator coupled to the decoder processor and configured to perform variable-length decoding operations on a variable-length code in the video data stream;wherein the variable-length decoding accelerator is configured by the decoder processor to decode a variable-length code according to any of a plurality of different decoding formats selected by the decoder processor based at least in part on a coding format of the video data stream; andwherein the variable-length decoding accelerator is configured to use for the selected decoding format a variable-length coding table of a plurality of different variable-length coding tables stored in memory that respectively correspond to the plurality of different decoding formats. 11. The system of claim 10 wherein each of the plurality of different variable-length coding tables matches variable-length codes to their corresponding decoded information. 12. The system of claim 10, wherein the variable-length decoding accelerator further comprises a register that dictates which of the plurality of different variable-length coding tables is to be utilized to decode the variable-length code, wherein the register is programmable to dictate the appropriate different variable-length coding table to be employed. 13. A video decoding system comprising: a decoder processor configured to perform decoding functions on a video data stream; anda hardware variable-length decoding accelerator external to the decoder processor and coupled to the decoder processor and configured to perform variable-length decoding operations on a variable-length code in the video data stream, wherein the variable-length decoding accelerator is configurable by the decoder processor to decode variable-length codes according to any of a plurality of different decoding formats selected by the decoder processor based at least in part on a coding format of the video data stream, wherein the hardware variable-length decoding accelerator includes a plurality of different variable-length coding tables stored in memory that respectively correspond to the plurality of different decoding formats. 14. The system of claim 13, wherein each of the plurality of different variable-length coding tables matches variable-length codes to their corresponding decoded information. 15. The system of claim 13, wherein the variable-length decoding accelerator further comprises a register that dictates which of the plurality of different variable-length coding tables is to be utilized to decode the variable-length code, wherein the register is programmable to dictate the appropriate different variable-length coding table to be employed. 16. A method, comprising: receiving, by a first variable-length decoding accelerator, a first macroblock data element in a video data stream from a decoder processor, the first macroblock data element comprising a first macroblock header and first coefficient data;receiving, by a second variable-length decoding accelerator, a second macroblock data element in the video data stream from the decoder processor, the second macroblock data element comprising a second macroblock header and second coefficient data;decoding, by the second variable-length decoding accelerator during a stage of decoding, the second coefficient data after decoding the second macroblock header; anddecoding, by the first variable-length decoding accelerator during the stage of decoding, the first macroblock header while the second variable-length decoding accelerator decodes the second coefficient data. 17. The method of claim 16, further comprising: receiving, by the second variable-length decoding accelerator, a third macroblock data element in the video data stream from the decoder processor, the third macroblock data element comprising a third macroblock header and third coefficient data;decoding, by the first variable-length decoding accelerator, the first coefficient data after decoding the first macroblock header; anddecoding, by the second variable-length decoding accelerator, the third macroblock header while the first variable-length decoding accelerator decodes the first coefficient data. 18. The method of claim 16, wherein each macroblock data element represents a macroblock of a video frame. 19. The method of claim 16, further comprising performing, by the decoder processor, decoding functions on the video data stream. 20. A method, comprising: receiving, by a video processing system, video data of a first coding format;configuring, by a decoder processor, a variable-length decoding accelerator of the video processing system to use a first variable-length coding table based at least in part on the first coding format;decoding the video data of the first coding format by the variable-length decoding accelerator;receiving, by the video processing system, video data of a second coding format differing from the first coding format;configuring, by the decoder processor, the variable-length decoding accelerator to use a second variable length coding table that is different from the first variable-length coding table based at least in part on the second coding format; anddecoding the video data of the second coding format by the variable-length decoding accelerator. 21. The method of claim 20, wherein configuring the variable-length decoding accelerator of the video processing system to use the first variable-length coding table further comprises setting a first value in a coding table selection register, the first value indicating the first variable-length coding table. 22. The method of claim 20, wherein the first coding format and the second coding format correspond to different discrete cosine transform (DCT)-based, variable-length coded, block-motion-compensated compression algorithms. 23. The system of claim 5, wherein the plurality of different decoding formats correspond to different compression algorithms. 24. The system of claim 10, wherein the plurality of different decoding formats correspond to different discrete cosine transform (DCT)-based compression standards.
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이 특허에 인용된 특허 (180)
Murphy Nicholas J. N.,GBX, 3D graphics object copying with reduced edge artifacts.
Raychaudhuri Dipankar (Princeton Junction NJ) Zdepski Joel W. (Lebanon NJ) Reitmeier Glenn A. (West Trenton NJ) Wine Charles M. (Princeton NJ), An HDTV compression system.
Cooper J. Carl (Monte Sereno CA) Wallen David (San Francisco CA) Vojnovic Mirko (Santa Clara CA) Loveless Howard (Ben Lomond CA), Apparatus and method for synchronizing asynchronous signals.
Drako Dean M. (Los Altos CA) Yu Hsiu-Tung A. (Palo Alto CA), Apparatus for manipulating image pixel streams to generate an output image pixel stream in response to a selected mode.
Clough Elizabeth A. (Menlo Park CA) Roskowski Steven G. (Sunnyvale CA) Perlman Stephen G. (Mountain View CA) Masterson Anthony D. (Cupertino CA), Apparatus for providing output filtering from a frame buffer storing both video and graphics signals.
Park Ju-ha (Suwon KRX) Jeon Byeung-woo (Sungnam KRX) Jeong Jechang (Seoul KRX), Apparatus for variable-length coding and variable-length-decoding using a plurality of Huffman coding tables.
Bates Cary L. (Rochester MN) Cragun Brian J. (Rochester MN) Donovan Robert J. (Rochester MN) Jaaskelainen William (Oronoco MN) Ryan Jeffrey M. (Byron MN) Striemer Bryan L. (Zumbrota MN), Aural position indicating mechanism for viewable objects.
Larson Michael Kerry ; McDonald Timothy James, Circuits systems and methods for managing data requests between memory subsystems operating in response to multiple address formats.
Gulick Dale ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system and method for transferring commands and data to a dedicated multimedia engine.
Mergard James Oliver ; Quimby Michael S. ; Wakeland Carl K., Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU.
Gulick Dale E. ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having a dedicated multimedia engine and multimedia memory having arbitration logic which grants main me.
Melo Maria L. ; Deschepper Todd ; Wilson Jeffrey T., Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base.
Gulick Dale E. ; Lambrecht Andy ; Webb Mike ; Hewitt Larry ; Barnes Brian, Computer system having separate digital and analog system chips for improved performance.
Salbaum Helmut,DEX ; Bauer Harald,DEX ; Fruhwald Friedrich,DEX, D.M.A. controller that determines whether the mode of operation as either interrupt or D.M.A. via single control line.
Boyce Jill M. (Manalapan NJ) Pearlstein Larry (Newton PA), Digital video decoder for decoding digital high definition and/or digital standard definition television signals.
Werner Ross G. (Woodside CA) Ryherd Eric L. (Brookline NH), Drawing processor for computer graphic system using a plurality of parallel processors which each handle a group of disp.
Alexander G. MacInnis ; Chengfuh Jeffrey Tang ; Xiaodong Xie ; James T. Patterson ; Greg A. Kranawetter, Graphics display system with color look-up table loading mechanism.
MacInnis Alexander G. ; Tang Chengfuh Jeffrey ; Xie Xiaodong ; Patterson James T. ; Kranawetter Greg A., Graphics display system with unified memory architecture.
Van Hook Timothy J. ; Cheng Howard H. ; DeLaurier Anthony P. ; Gossett Carroll P. ; Moore Robert J. ; Shepard Stephen J. ; Anderson Harold S. ; Princen John ; Doughty Jeffrey C. ; Pooley Nathan F. ; , High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing.
Shibata Hideaki (Osaka JPX) Bannai Tatsushi (Sakai JPX), High-efficiency coding apparatus for compressing a digital video signal while controlling the coding bit rate of the com.
Lum Sanford S.,CAX ; Chen Keping,CAX ; Wong Samuel L. C.,CAX ; Bennett Dwayne R.,CAX ; Alford Michael A.,CAX, Host CPU independent video processing unit.
Borrel Paul ; Cheng Keh-Shin Fu ; Menon Jai Prakash ; Rossignac Jaroslaw Roman, Hotlinks between an annotation window and graphics window for interactive 3D graphics.
Miyuki Enokida JP; Tadashi Yoshida ; Kunihiro Yamamoto JP, Information processing method and apparatus for displaying a list of a plurality of image data files and a list of search results.
Rhodes Kenneth E. (Portland OR) Adams Robert T. (Lake Oswego OR) Janes Sherman (Portland OR) Coelho Rohan G. F. (Hillsboro OR), Integrated graphics and video computer display system.
Fandrianto Jan ; Martin Bryan R. ; Neubauer Doug G. ; Tran Duat H. ; Cressa Matthew D. ; Soemedi Arijanto, Integrated multimedia communications processor and codec.
Crochiere Ronald Eldon (Chatham NJ) Rabiner Lawrence Richard (Berkeley Heights NJ), Interpolation-decimation circuit for increasing or decreasing digital sampling frequency.
Nachtergaele Lode J.M.,BEX ; Catthoor Francky,BEX ; Kapoor Bhanu ; Janssens Stefan,BEX, Low power video decoder system with block-based motion compensation.
Carini Richard P. (Kingston NY) Donnelly James A. (West Hurley NY) Ellis ; Jr. Joseph J. (West Hurley NY) Lanzoni Thomas P. (Kingston NY), Merged data storage panel display.
Jouppi Norman P. ; McCormack Joel J. ; Chang Chun-Fa, Method and apparatus for compositing colors of images with memory constraints for storing pixel data.
Rhodes Ken (Portland OR) Coelho Rohan (Hillsboro OR) Frank Davis (Beaverton OR) Bender Blake (Beaverton OR), Method and apparatus for displaying an image in a windowed environment.
Gough Michael L. (Ben Lomond CA) Venolia Daniel S. (Foster City CA) Gilley Thomas S. (Pleasanton CA) Robbins Greg M. (Cupertino CA) Hansen ; Jr. Daniel J. (Cupertino CA) Oswal Abhay (Fremont CA) Tam , Method and apparatus for displaying an overlay image.
Dilliplane Stephen C. ; Lavelle Gary J. ; Maino James G. ; Selvaggi Richard J. ; Tseng Jack, Method and apparatus for displaying multiple windows on a display monitor.
Mills Karl Scott ; Holmes Jeffrey Michael ; Bonnelycke Mark Emil ; Owen Richard Charles Andrew, Method and apparatus for executing a raster operation in a graphics controller circuit.
Garrison John Michael ; Wilson Gale Arthur, Method and apparatus for manipulating very long lists of data displayed in a graphical user interface using a layered li.
Gough Michael L. ; MacDougald Joseph J. ; Venolia Daniel S. ; Gilley Thomas S. ; Robbins Greg M. ; Hansen ; Jr. Daniel J. ; Oswal Abhay, Method and apparatus for providing translucent images on a computer display.
Chow Paul,CAX ; Mizuyabu Carl K.,CAX ; Swan Philip L.,CAX ; Porter Allen J.C.,CAX ; Wang Chun,CAX, Method and apparatus for storing and displaying video image data in a video graphics system.
Gandhi Bhavan R. ; Smith Craig Michael,JPX ; Sullivan James R. ; Couwenhoven Douglas W. ; Rombola Gregory, Method for adaptively compressing residual digital image data in a DPCM compression system.
MacInnis, Alexander G.; Hsiun, Vivian; Zhong, Sheng; Xie, Xiaodong; So, Kimming; Alvarez, Jose′ R., Method of communicating between modules in a decoding system.
Yokota Teppei (Chiba JPX) Aramaki Junichi (Chiba JPX) Kihara Nobuyuki (Tokyo JPX), Method of recording on a recording medium employing an automatic updating of management data by monitoring the signal be.
King Sherman T. (San Francisco CA) Lee Tommy C. (Danville CA) Wang Niantsu (Milpitas CA) Chu Yen-Fah (San Jose CA) Kimura Scott A. (San Jose CA) Hwang Guorjuh T. (Milpitas CA), Multimedia overlay system for graphics and video.
Cottle Temple D. ; Spits Tiemen T., Programmable interrupt controller with interrupt set/reset register and dynamically alterable interrupt mask for a single interrupt processor.
Ogrinc Michael A. (San Francisco CA) Card Robert A. (Palo Alto CA) Burns Chris R. (Mountain View CA) Clarke Charles P. (Los Altos CA) Collier Ronda L. (Scotts Valley CA) Collins Kevin M. (San Mateo C, Real time video image processing system.
Slattery William ; Gratacap Regis, Remultipelxer cache architecture and memory organization for storing video program bearing transport packets and descriptors.
Fielder Dennis (Linton GBX) Derbyshire James (Willingham GBX) Gillingham Peter (Kanata CAX) Torrance Randy (Ottawa CAX) O\Connell Cormac (Kanata CAX), Single chip frame buffer and graphics accelerator.
Crinon Regis J. ; Sezan Muhammed Ibrahim, Sprite-based video coding system with automatic segmentation integrated into coding and sprite building processes.
Ke Ligang ; Lutz Juergen M., System and method for utilizing a two-dimensional adaptive filter for reducing flicker in interlaced television images converted from non-interlaced computer graphics data.
Priem Curtis ; Rosenthal David S. H., System for providing fast transfers to input/output device by assuring commands from only one application program reside in FIFO.
Washington Emanuel ; Perkins Mike ; Johnson Brian ; How Stephen ; Daines Nolan ; Ayers Tom ; Vertrees Keith, Transport stream decoder/demultiplexer for hierarchically organized audio-video streams.
Timothy J. Van Hook ; Howard H. Cheng ; Anthony P. DeLaurier ; Carroll P. Gossett ; Robert J. Moore ; Stephen J. Shepard ; Harold S. Anderson ; John Princen ; Jeffrey C. Doughty ; Nathan F. , Video game system and coprocessor for video game system.
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