[특허]Software-to-hardware compiler with symbol set inference analysis

Software-to-hardware compiler with symbol set inference analysis 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/45 G06F-017/50
출원번호	US-0613581 (2012-09-13)
등록번호	US-8930922 (2015-01-06)
발명자 / 주소	Metzgen, Paul
출원인 / 주소	Altera Corporation
인용정보	피인용 횟수 : 0 인용 특허 : 66

초록 ▼

A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.

대표청구항 ▼

1. A method for converting software source code for a program into hardware constructs, the method comprising: identifying a set of potentially recursive functions defined in the software source code, wherein each function in the identified set is configured to receive arguments;generating a new function based on the functions in the identified set, wherein the new function substitutes global variables for the arguments of each function in the identified set;generating a plurality of stacks, wherein each of the plurality of stacks is associated with a respective one of the functions in the identified set, and wherein each of the plurality of stacks stores the global variables corresponding to the function arguments, local variables, a return value, and a return address; andgenerating a plurality of stack pointers, wherein each of the plurality of stack pointers is associated with a respective one of the plurality of stacks, and wherein each of the plurality of stack pointers points to the one of the plurality of stacks with which it is associated. 2. The method of claim 1 further comprising accessing more than one of the plurality of stacks a single clock cycle during run-time to facilitate parallel processing. 3. The method of claim 1 wherein generating a plurality of stacks comprises generating a plurality of stacks, wherein each of the plurality of stacks is allocated a data width that minimizes hardware resources used. 4. The method of claim 1 further comprising generating the new function in a form that allows for easier symbol set inference analysis. 5. The method of claim 1 further comprising performing symbol set inference analysis to optimize the size of each of the plurality of stacks. 6. The method of claim 1 further comprising replacing each function in the identified set with a corresponding label, wherein the labels are included in the new function. 7. A method for compiling a redirection statement in software source code for a program, which is used to redirect execution to a particular destination in the software source code, into hardware constructs using a software-to-hardware compiler, the method comprising: generating a variable;initializing the variable to a first value corresponding to a loop mode;executing the program until the redirection statement is reached, wherein the redirection statement identifies the particular destination;assigning to the variable a second value corresponding to the particular destination;traversing statements after the redirection statement until one of (i) a statement corresponding to the second value of the variable and (ii) an end of a function is reached, wherein statements that do not correspond to the second value of the variable are not executed;when the end of the function is reached prior to reaching a statement corresponding to the second value of the variable, traversing statements starting from the beginning of the function without executing the statements until a statement corresponding to the second value of the variable is reached; andassigning to the variable the first value when the statement corresponding to the second value of the variable is reached. 8. A non-transitory computer-readable medium comprising computer-readable instructions for a software-to-hardware compiler that converts software source code for a program into hardware constructs, the software-to-hardware compiler configured to: identify a set of potentially recursive functions defined in the software source code, wherein each function in the identified set is configured to receive arguments;generate a new function based on the functions in the identified set, wherein the new function substitutes global variables for the arguments of each function in the identified set; andprogram the hardware to: generate a plurality of stacks, wherein each of the plurality of stacks is associated with a respective one of the functions in the identified set, and wherein each of the plurality of stacks stores the global variables corresponding to the function arguments, local variables, a return value, and a return address; andgenerate a plurality of stack pointers, wherein each of the plurality of stack pointers is associated with a respective one of the plurality of stacks, and wherein each of the plurality of stack pointers points to the one of the plurality of stacks with which it is associated. 9. The non-transitory computer-readable medium of claim 8 wherein the hardware is configured to access more than one of the plurality of stacks in a single clock cycle to facilitate parallel processing. 10. The non-transitory computer-readable medium of claim 8 wherein each of the plurality of stacks is allocated a data width that minimizes hardware resources used. 11. The non-transitory computer-readable medium of claim 8 wherein the new function is generated in a form that allows for easier symbol set inference analysis. 12. The non-transitory computer-readable medium of claim 8 wherein the software-to-hardware compiler is further configured to perform symbol set inference analysis to optimize the size of each of the plurality of stacks. 13. The non-transitory computer-readable medium of claim 8 wherein the software-to-hardware compiler is further configured to replace each function in the identified set with a corresponding label, wherein the labels are included in the new function.

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Sharrit Paul ; Campini Edoardo ; Cornils Curtis L., Communicator having reconfigurable resources.
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Guccione Steven A. ; Levi Delon, Configuration of programmable logic devices with routing core generators.
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Arora, Ken; Sharangpani, Harshvardhan; Gupta, Rajiv, Copied register files for data processors having many execution units.
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Edwards,Stephen G.; Davis,Donald J.; Harris,Jonathan C.; Jensen,James E.; Kollegger,Andreas B.; Miller,Ian D., Determining hardware generated by high level language compilation through loop optimizations.
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Alkalaj Leon ; Fang Wai-Chi ; Newell Michael A., Electronic processing and control system with programmable hardware.
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Chun Robert K. (Fullerton CA), Expert system compilation method.
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Southgate Timothy James, FPGA based configurable CPU additionally including second programmable section for implementation of custom hardware su.
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Baker Henry G. (16231 Meadow Ridge Way Encino CA 91436), Garbage collection, tail recursion and first-class continuations in stack-oriented languages.
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Razdan Rahul ; Smith Michael D., Hardware extraction technique for programmable reduced instruction set computers.
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Kean Thomas A. (Edinburgh GB6), Hierarchically connectable configurable cellular array.
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Esposito,Benjamin; Pelt,Robert L, Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry.
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Taylor Brad (Oakland CA), Implementation of a selected instruction set CPU in programmable hardware.
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Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
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Levin Roy (Palo Alto CA) Hanna Christine B. (Woodside CA), Language scoping for modular, flexible, concise, configuration descriptions.
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Rostoker Michael D. (Boulder Creek CA) Dangelo Carlos (Los Gatos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
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Gokhale, Maya B.; Stone, Janice M.; Riganati, John P., Method for determining an optimal partitioning of data among several memories.
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Miller,Ian D.; Edwards,Stephen G.; Harris,Jonathan C.; Jensen,James E.; Kollegger,Andreas B.; Schanck,Christopher R. S.; Wu,Conor C., Method of transforming software language constructs to functional hardware equivalents.
상세보기
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Robinson Jeffrey I. (New Fairfield CT), Programmable integrated circuit using topological and parametric data to selectively connect and configure different hig.
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Taylor Brad, Programmable logic device for real time video processing.
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Kean Thomas A.,GB6, Programmable switch for FPGA input/output signals.
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Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
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Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
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Smith, Stephen J.; Southgate, Timothy J., Reconfigurable programmable logic device computer system.
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Madurawe Raminda (Sunnyvale CA), Reconfigurable programmable logic device having static and non-volatile memory.
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Koichi Sato JP; Lcu Semeria ; Giovanni De Micheli, Resolution of dynamic memory allocation/deallocation and pointers.
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Edwards,Stephen G.; Davis,Donald J.; Harris,Jonathan C.; Kollegger,Andreas B.; Miller,Ian D.; Schanck,Christopher R. S.; Yu,Yung Sheng, Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations.
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Anderson Forrest (P.O. Box 1400 Bernalillo NM 87004), Single pulse imaging device.
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Roohparvar, Frankie F., Synchronous flash memory with accessible page during write.
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Roohparvar, Frankie F., Synchronous flash memory with simultaneous access to one or more banks.
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Dice David ; Herrick Andrew F. ; Mann Ronald J., System and method for automatically and selectively promoting object variables to method fields and variables in a digital computer system.
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Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Mihal, Andrew, System and method for configuring a programmable hardware instrument to perform measurement functions utilizing estimation of the hardware implentation and management of hardware resources.
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Kodosky Jeffrey L. ; Andrade Hugo ; Odom Brian K. ; Butler Cary P., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
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Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware.
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Lacey Steve,GB2, System and method for parsing and executing a single instruction stream using a plurality of tightly coupled parsing and.
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Benson Thomas R. (Hollis NH), Tracking condition codes in translation code for different machine architectures.
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Kolchinsky Alexander (48 Gray Rd. Andover MA 01810), Virtual processor module including a reconfigurable programmable matrix.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Software-to-hardware compiler with symbol set inference analysis 원문보기

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Software-to-hardware compiler with symbol set inference analysis 원문보기

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연구과제 타임라인

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