Method of manufacturing a semiconductor device with two monocrystalline layers
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/20
H01L-021/84
H01L-021/268
H01L-021/683
H01L-021/762
H01L-021/822
H01L-027/06
H01L-027/108
H01L-027/11
H01L-027/115
H01L-027/12
H01L-027/22
H01L-027/24
H01L-029/78
H01L-027/105
H01L-045/00
출원번호
US-0246157
(2011-09-27)
등록번호
US-8956959
(2015-02-17)
발명자
/ 주소
Sekar, Deepak C.
Or-Bach, Zvi
출원인 / 주소
Monolithic 3D Inc.
인용정보
피인용 횟수 :
4인용 특허 :
342
초록▼
A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after
A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after the first monocrystalline layer has been formed; transferring the second monocrystalline layer overlying the isolation layer; and then performing a second lithography step patterning portions of the first monocrystalline layer as part of forming at least one transistor in the first monocrystalline layer.
대표청구항▼
1. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising: providing a first monocrystalline layer;patterning said first monocrytalline layer;overlaying said first monocrystalline layer with an isolation layer;preparing a second monocrystalline layer, a
1. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising: providing a first monocrystalline layer;patterning said first monocrytalline layer;overlaying said first monocrystalline layer with an isolation layer;preparing a second monocrystalline layer, after said first monocrystalline layer has been formed;transferring said second monocrystalline layer using ion-cut, said second monocrystalline layer overlying said isolation layer; andafter transferring said second monocrystalline layer, etching portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer. 2. A method of manufacturing a semiconductor wafer according to claim 1, wherein said at least one transistor is part of a volatile memory cell. 3. A method of manufacturing a semiconductor wafer according to claim 1, wherein said at least one transistor is part of an RRAM (Resistor Random Access Memory) or Phase Change memory cell. 4. A method of manufacturing a semiconductor wafer according to claim 1, wherein said at least one transistor is part of a charge trap memory cell. 5. A method of manufacturing a semiconductor wafer according to claim 1, further comprising: constructing memory peripheral circuits underneath or overlaying said at least one transistor. 6. A method of manufacturing a semiconductor wafer according to claim 5, wherein at least one memory select line is embedded in said second monocrystalline layer. 7. A method of manufacturing a semiconductor wafer according to claim 1, wherein said second monocrystalline layer comprises memory cells, andwherein said memory cells are of a DRAM, a resistive-RAM, or a phase-change type. 8. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising: providing a first monocrystalline layer comprising semiconductor regions defined by a first lithography step; thenoverlaying said first monocrystalline layer with an isolation layer;preparing a second monocrystalline layer, after said first monocrystalline layer has been formed;transferring said second monocrystalline layer overlying said isolation layer; and thenperforming a second lithography step patterning portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer. 9. A method of manufacturing a semiconductor wafer according to claim 8, wherein said at least one transistor is part of an RRAM (Resistor Random Access Memory) or Phase Change memory cell. 10. A method of manufacturing a semiconductor wafer according to claim 8, wherein said at least one transistor is part of a volatile memory cell. 11. A method of manufacturing a semiconductor wafer according to claim 8, wherein said at least one transistor is part of a charge trap memory cell. 12. A method of manufacturing a semiconductor wafer according to claim 8, further comprising: constructing memory peripheral circuits underneath or overlaying said at least one transistor. 13. A method of manufacturing a semiconductor wafer according to claim 12, wherein at least one memory select line is embedded in said second monocrystalline layer. 14. A method of manufacturing a semiconductor wafer according to claim 8wherein said second monocrystalline layer comprises memory cells, andwherein said memory cells are of a DRAM, a resistive-RAM, or a phase-change type. 15. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising: providing a first monocrystalline layer;patterning said first monocrystalline layer;overlaying said first monocrystalline layer with an isolation layer;preparing a second monocrystalline layer after said first monocrystalline layer has been formed, said second monocrystalline layer overlying said isolation layer; andafter forming said second monocrystalline layer, etching portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer, wherein said second monocrystalline layer comprises memory cells, andwherein said memory cells are of a volatile type. 16. A method of manufacturing a semiconductor wafer according to claim 15, wherein said at least one transistor is part of a volatile memory cell. 17. A method of manufacturing a semiconductor wafer according to claim 15, wherein said at least one transistor is part of an RRAM (Resistor Random Access Memory) or Phase Change memory cell. 18. A method of manufacturing a semiconductor wafer according to claim 15, wherein at least one memory select line is embedded in said second monocrystalline layer. 19. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising: providing a first monocrystalline layer;patterning said first monocrystalline layer;overlaying said first monocrystalline layer with an isolation layer;preparing a second monocrystalline layer after said first monocrystalline layer has been formed, said second monocrystalline layer overlying said isolation layer; andafter forming said second monocrystalline layer, lithographically patterning portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer, wherein said second monocrystalline layer comprises memory cells, andwherein said memory cells are of a DRAM, a resistive-RAM, or a phase-change type. 20. A method of manufacturing a semiconductor wafer according to claim 19, wherein said at least one transistor is part of a volatile memory cell. 21. A method of manufacturing a semiconductor wafer according to claim 19, wherein said preparing a second monocrystalline layer comprises an ion-cut layer transfer. 22. A method of manufacturing a semiconductor wafer according to claim 19, further comprising: constructing memory peripheral circuits underneath or overlaying said at least one transistor. 23. A method of manufacturing a semiconductor wafer according to claim 19, wherein at least one memory select line is embedded in said second monocrystalline layer.
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