초록 ▼

A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The

A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

대표청구항 ▼

1. A silicon chip comprising: a trenched MIM capacitor comprising:a silicon substrate layer having a bottom side and a top side, a portion of the top side defining a plurality of trenches;a first MIM capacitor stack covering the portion of the top side; anda first conductive compressive material lay

1. A silicon chip comprising: a trenched MIM capacitor comprising:a silicon substrate layer having a bottom side and a top side, a portion of the top side defining a plurality of trenches;a first MIM capacitor stack covering the portion of the top side; anda first conductive compressive material layer substantially covering the first MIM capacitor stack,wherein the first conductive compressive material layer comprises Poly-SixGe1-x. 2. The silicon chip of claim 1, wherein the first conductive compressive material layer fills the plurality of trenches. 3. The silicon chip of claim 1, wherein the trenched MIM capacitor further comprises: a second MIM capacitor stack covering at least a portion of the first conductive compressive material layer, anda second conductive compressive material layer substantially covering the second MIM capacitor stack. 4. The silicon chip of claim 1, further comprising a compressive passivation oxide layer that substantially covers an upper surface of the plurality of trenched MIM capacitors. 5. The silicon chip of claim 1, further comprising a tensile material layer on the bottom side. 6. The silicon chip of claim 1, wherein the silicon chip is part of a silicon wafer. 7. The silicon chip of claim 1, further comprising a third conductive compressive material layer between the top side and the first MIM capacitor stack. 8. The silicon chip of claim 1, wherein the first MIM capacitor stack comprises a first Hi-k layer between a first TiN layer and a second TiN layer. 9. A silicon wafer comprising a silicon chip portion, the silicon chip portion comprises an array of deep trenches; the array of deep trenches define a deep trench MIM capacitor comprising: a silicon substrate having a top surface that defines a trench therein;a first MIM stack layer overlaid on the top surface; anda first conductive compressive material layer overlaid on the first MIM stack layer,wherein the first conductive compressive layer comprises Poly-SixGe1-x, wherein a 0.2