Apparatus and method for configurable processing
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-015/80
G06F-015/78
G06F-009/30
G06F-009/38
출원번호
US-0122385
(2005-05-05)
등록번호
US-8966223
(2015-02-24)
발명자
/ 주소
Knowles, Simon
출원인 / 주소
Icera, Inc.
인용정보
피인용 횟수 :
1인용 특허 :
14
초록▼
A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, each module being connectable to receive input operands indicated
A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, each module being connectable to receive input operands indicated in an instruction, and a programmable lookup table connectable to receive dynamic configuration information determined from an opcode portion of the instruction and capable of generating operator configuration settings defining an aspect of the function or behavior of a configurable operator module, responsive to said dynamic configuration information in the instruction.
대표청구항▼
1. A computer processor comprising: an instruction memory comprising instructions making up an instruction set for the processor, wherein the instruction set includes data processing instructions, each data processing instruction comprising an opcode portion carrying dynamic configuration informatio
1. A computer processor comprising: an instruction memory comprising instructions making up an instruction set for the processor, wherein the instruction set includes data processing instructions, each data processing instruction comprising an opcode portion carrying dynamic configuration information and operand data portion;a decode unit comprising control circuitry configured to receive and decode a sequence of instructions supplied from the instruction memory, including said data processing instructions, and control the components of the processor in accordance with each of the decoded instructions;a configurable execution unit comprising operators capable of being dynamically configured at the level of processing multi-bit operand values, on an instruction by instruction basis, responsive to the configuration information carried in the opcode portion of each data-processing instruction, wherein said operators are provided in one or more dynamically configurable operator modules, said operators being configured to separately receive (i) at least one input operand responsive to the operand data in said data processing instruction and (ii) operator configuration settings defining aspects of the function and/or behavior of said configurable operator module at the level of processing multi-bit operands, wherein said operator configuration settings are derived from the dynamic configuration information carried in the opcode portion of said data processing instruction and wherein said execution unit comprises a configurable switching fabric having connectivity defined at least in part by pseudo static control information provided independently of the instruction carrying the dynamic configuration information and; anda programmable look up table that comprises said pseudo static control information and configured to receive said dynamic configuration information from the opcode portion of respective data processing instructions and being adapted translate said dynamic configuration information into operator configuration settings applying to said configurable operators. 2. The computer processor of claim 1, wherein said programmable lookup table comprises a programmable logic array. 3. The computer processor of claim 2, wherein said programmable lookup table comprises cascaded programmable logic arrays. 4. The computer processor of claim 1, wherein said configurable switching fabric comprises one or more of: a configurable input interconnect means connected upstream of the configurable operators and a configurable output interconnect means connected downstream of the configurable operators. 5. The computer processor of claim 4, wherein said configurable switching fabric comprises configurable input interconnect means connected upstream of the configurable operators and configurable output interconnect means connected downstream of said configurable operators. 6. The computer processor of claim 5, wherein one or more outputs of one or more configurable operator modules is connected to said configurable input interconnect means. 7. The computer processor of claim 1, wherein at least one configurable operator module is hard-wired to support a predetermined class of operation and is dynamically configurable by operator configuration settings to adjust operator function and/or behaviour within said general operation class. 8. The computer processor of claim 1, wherein said operators comprise a module with configurable shift and/or permute functionality. 9. The computer processor of claim 1, wherein said pseudo static control information is provided independently of the instruction carrying the dynamic configuration information. 10. The computer processor of claim 9, wherein one or more components include thereon pseudo static control information established by configuration setting instructions. 11. The computer processor of claim 1, comprising a plurality of dynamically configurable operators configurable by means of configuration information provided in a data processing instruction, wherein, in use, an operator configuration according to said configuration information acts on operands indicated in said data processing operation. 12. The computer processor of claim 1, comprising one or more dynamically configurable operators configurable by means of configuration information provided in a data processing instruction, wherein, in use, an operator configuration according to said configuration information acts on operands indicated in a subsequent instruction. 13. The computer processor of claim 1, capable in response to a single instruction of performing two or more sequential, selectively configurable operations on an operand before outputting results. 14. The computer processor of claim 1, wherein one or more of said configurable operator modules supports SIMD operations. 15. The computer processor of claim 1, comprising operators in one or more of the following operator classes: multiplier, arithmetic logic, storage, shift and/or permute. 16. The computer processor of claim 1, wherein the programmable lookup table generates operator configuration settings selected from one or more of: a carry-in signal; a multiplexer selection; a negotiable input; an overflow setting; and other suitable inputs of operators. 17. The computer processor of claim 1, wherein the programmable lookup table receives one or more inputs from one or more dynamically configurable operator modules. 18. The computer processor of claim 17, wherein the input from the dynamically configurable operator module comprises one or more selected from: an overflow indication; a FIFO full signal; a Boolean result of arithmetic comparison; and other suitable outputs of operators. 19. The computer processor of claim 1, wherein the programmable lookup table comprises different pseudo static control information. 20. A computer processor method for use comprising: storing instructions in an instruction memory that make up an instruction set for the processor, wherein the instruction set includes data processing instructions, each data processing instruction comprising an opcode portion carrying dynamic configuration information and operand data portion;receiving and decoding in a decode unit having control circuitry a sequence of instructions supplied from the instruction memory, including said data processing instructions,controlling the components of the processor in accordance with each of the decoded instructions;dynamically configuring a configurable execution unit with operators configured at the level of processing multi-bit operand values, on an instruction by instruction basis, responsive to the configuration information carried in the opcode portion of each data-processing instruction, wherein said operators are provided in one or more dynamically configurable operator modules, said operators being configured to separately receive (i) at least one input operand responsive to the operand data in said data processing instruction and (ii) operator configuration settings defining aspects of the function and/or behaviour of said configurable operator module at the level of processing multi-bit operands, wherein said operator configuration settings are derived from the dynamic configuration information carried in the opcode portion of said data processing instruction and wherein said execution unit connects through configurable switching fabric defined at least in part by pseudo static control information provided independently of the instruction carrying the dynamic configuration information;receiving in a programmable look up the table said dynamic configuration information from the opcode portion of respective data processing instructions;translating in the programmable look up table said dynamic configuration information into operator configuration settings applying to said configurable operators, wherein the programmable look up table comprises the pseudo static control information. 21. The method according to claim 20, wherein a sequence of two or more operations are performed in series responsive to the instruction. 22. The method according to claim 20, wherein two or more operations are performed in parallel responsive to the instruction. 23. The method according to claim 20, wherein a combination of series and parallel operations is performed responsive to the instruction. 24. The method according to claim 20, wherein a plurality of series and/or parallel operations are performed responsive to the instruction and at least one intermediate result is held in a storage operator between operations or before being * output from the configurable execution unit to a result store. 25. The method according to claim 20, wherein a—plurality of series and/or parallel operations are performed responsive to the instruction and wherein an intermediate result is shifted or permuted between operations or before being output from the configurable execution unit to a result store.
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이 특허에 인용된 특허 (14)
DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.
Trimberger Stephen M., Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution.
Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Jon M. Huppenthal ; Paul A. Leskar, Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer.
Nickolls, John R.; Johnson, Scott D.; Williams, Mark; Mirsky, Ethan; Kirthiranjan, Kambdur; Pant, Amrit Raj; Madar, III, Lawrence J., Reconfigurable processing system and method.
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