Detector array for high speed sampling of an optical pulse
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01C-003/08
G06M-007/00
G01S-007/486
G01S-017/89
출원번호
US-0776094
(2010-05-07)
등록번호
US-9052381
(2015-06-09)
발명자
/ 주소
Woolaway, James T.
Schlesselmann, John D.
출원인 / 주소
FLIR Systems, Inc.
대리인 / 주소
Haynes and Boone, LLP
인용정보
피인용 횟수 :
4인용 특허 :
30
초록▼
Various techniques are provided for performing detection using a focal plane array (FPA). For example, in one embodiment, a unit cell of an FPA may be implemented to support rapid sampling in response to one or more laser pulses reflected from an object or feature of interest. An FPA implemented wit
Various techniques are provided for performing detection using a focal plane array (FPA). For example, in one embodiment, a unit cell of an FPA may be implemented to support rapid sampling in response to one or more laser pulses reflected from an object or feature of interest. An FPA implemented with such unit cells may be used, for example, in an imaging system capable of detecting a plurality of two dimensional image frames and providing a three dimensional image using the detected two dimensional image frames. Other applications of such rapid sampling unit cells are also contemplated.
대표청구항▼
1. A focal plane array (FPA) comprising: a plurality of unit cells arranged in a plurality of rows and a plurality of columns, each unit cell of the FPA comprising: a detector comprising a diode adapted to provide a current in response to an optical pulse received by the detector; anda first circuit
1. A focal plane array (FPA) comprising: a plurality of unit cells arranged in a plurality of rows and a plurality of columns, each unit cell of the FPA comprising: a detector comprising a diode adapted to provide a current in response to an optical pulse received by the detector; anda first circuit comprising: an integrator circuit comprising: an input node adapted to receive the current from the detector,an output node,a source follower amplifier connected between the input node and the output node and adapted to provide a first voltage at the output node that changes in response to the current received at the input node, anda first switch adapted to selectively set the input node to a reset voltage before the current is received from the detector;a sample and hold (S/H) circuit comprising a first capacitor and a second switch, wherein the first capacitor comprises a first terminal connected to a reference voltage and a second terminal connected to the second switch, wherein the S/H circuit is adapted to sample a second voltage across the first capacitor using the second switch, wherein the second voltage is associated with the first voltage;a correlated double sampling (CDS) circuit connected to the integrator circuit and the S/H circuit and adapted to set the second terminal of the first capacitor to the reference voltage and then provide the second voltage to the second terminal of the first capacitor;a buffer adapted to provide the second voltage to be read out from the unit cell; andwherein at least one of the detectors and at least one of the first circuits is provided for each unit cell of the FPA. 2. The FPA of claim 1, wherein the second switch is adapted to selectively connect the first capacitor to the CDS circuit, wherein the CDS circuit comprises a third switch adapted to set the first capacitor to the reference voltage before the second voltage is received at the first capacitor through the second switch. 3. The FPA of claim 2, wherein the S/H circuit is adapted to sample a plurality of voltages associated with values of the first voltage at a plurality of time intervals associated with a plurality of optical pulses. 4. The FPA of claim 1, each unit cell further comprising a summing amplifier circuit connected to the integrator circuit and the S/H circuit, wherein the summing amplifier circuit is adapted to integrate the first voltage over a plurality of optical pulses to provide the second voltage to the first capacitor. 5. The FPA of claim 4, wherein the summing amplifier circuit comprises: an amplifier;a third switch adapted to selectively reset the amplifier;a second capacitor; anda fourth switch adapted to selectively connect the second capacitor in a feedback path of the amplifier to integrate the first voltage across the second capacitor. 6. The FPA of claim 1, wherein the S/H circuit is further adapted to sample a plurality of voltages associated with values of the first voltage at a plurality of time intervals associated with the optical pulse. 7. The FPA of claim 6, wherein the S/H circuit further comprises: a plurality of capacitors; anda plurality of switches adapted to selectively connect corresponding capacitors of the plurality of capacitors to the integrator circuit at corresponding time intervals of the plurality of time intervals to sample the plurality of voltages. 8. The FPA of claim 6, each unit cell further comprising: a plurality of delay taps adapted to provide a plurality of control signals to the S/H circuit to sample the voltages at the time intervals; anda plurality of transistors adapted to be operated to selectively adjust the time intervals by adjusting a plurality of delay times associated with the delay taps. 9. The FPA of claim 1, wherein the diode is a reverse-biased PIN diode. 10. The FPA of claim 1, wherein the optical pulse is a reflected laser pulse, wherein the second voltage corresponds to a value associated with one of a plurality of pixels of the FPA. 11. A method of operating a unit cell of a focal plane array (FPA), wherein the FPA comprises a plurality of the unit cells, the method comprising: setting an input node of an integrator circuit to a reset voltage by operating a first switch;detecting an optical pulse using a diode;providing a current to the input node in response to the detecting, wherein the current causes the input node to adjust from the reset voltage to an input voltage;providing a first voltage at an output node of the integrator circuit based on the input voltage;sampling, by a sample and hold (S/H) circuit, a second voltage across a first capacitor using a second switch of the S/H circuit, wherein the first capacitor comprises a first terminal connected to a reference voltage and a second terminal connected to the second switch, wherein the second voltage is associated with the first voltage;operating a correlated double sampling (CDS) circuit by: setting the second terminal of the first capacitor to the reference voltage, andproviding the second voltage to the second terminal of the first capacitor after the second terminal of the first capacitor is set to the reference voltage;providing, by a buffer, the second voltage to be read out from the unit cell;wherein the unit cells are arranged in a plurality of rows and a plurality of columns;wherein the integrator circuit, the S/H circuit, the CDS circuit, and the buffer are provided by a first circuit; andwherein at least one of the diodes and at least one of the first circuits is provided for each unit cell of the FPA. 12. The method of claim 11, further comprising: sampling a plurality of voltages associated with values of the first voltage at a plurality of time intervals associated with a plurality of optical pulses; andproviding the plurality of voltages to be read out from the unit cell. 13. The method of claim 11, further comprising integrating the first voltage over a plurality of optical pulses to provide the second voltage to the capacitor. 14. The method of claim 13, wherein the integrating comprises performing the following for each optical pulse of a plurality of optical pulses: resetting an amplifier;connecting a second capacitor in a feedback path of the amplifier;integrating the first voltage across the second capacitor; anddisconnecting the second capacitor from the feedback path. 15. The method of claim 11, further comprising sampling a plurality of voltages associated with values of the first voltage at a plurality of time intervals associated with the optical pulse. 16. The method of claim 15, further comprising: providing a plurality of control signals to sample the voltages at the time intervals; andselectively adjusting the time intervals. 17. The method of claim 11, wherein the diode is a reverse-biased PIN diode. 18. The method of claim 11, wherein the optical pulse is a reflected laser pulse, wherein the second voltage corresponds to a value associated with one of a plurality of pixels of the FPA. 19. A focal plane array (FPA) comprising a plurality of unit cells, each unit cell of the FPA comprising: means for setting an input node of an integrator circuit to a reset voltage;means for detecting an optical pulse;means for providing a current to the input node in response to the detecting means, wherein the current causes the input node to adjust from the reset voltage to an input voltage;means for providing a first voltage at an output node of the integrator circuit based on the input voltage;means for sampling a second voltage associated with the first voltage, wherein the sampling means comprises: a switch, and a capacitor comprising a first terminal connected to a reference voltage and a second terminal connected to the switch;means for setting the second terminal of the capacitor to the reference voltage;means for providing the second voltage to the sampling means after the sampling means is set to the reference voltage;means for providing the second voltage to be read out from the unit cell;wherein the unit cells are arranged in a plurality of rows and a plurality of columns;wherein the integrator circuit, the sampling means, the reference voltage setting means, and the second voltage providing means are provided by a first circuit; andwherein at least one of the detecting means and at least one of the first circuits is provided for each unit cell of the FPA. 20. The FPA of claim 19, each unit cell further comprising: means for sampling a plurality of voltages associated with values of the first voltage at a plurality of time intervals associated with a plurality of optical pulses; andmeans for providing the plurality of voltages to be read out from the unit cell. 21. The FPA of claim 19, each unit cell further comprising means for integrating the first voltage over a plurality of optical pulses to provide the second voltage to the sampling means. 22. The FPA of claim 19, each unit cell further comprising means for sampling a plurality of voltages associated with values of the first voltage at a plurality of time intervals associated with the optical pulse. 23. The FPA of claim 22, each unit cell further comprising: means for providing a plurality of control signals to sample the voltages at the time intervals; andmeans for selectively adjusting the time intervals. 24. The FPA of claim 19, wherein the optical pulse is a reflected laser pulse, wherein the second voltage corresponds to a value associated with one of a plurality of pixels of the FPA.
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