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Interrupt handling techniques in the rasterizer of a GPU 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06T-001/00
  • G06T-015/00
  • G06F-009/48
출원번호 US-0002727 (2007-12-17)
등록번호 US-9064333 (2015-06-23)
발명자 / 주소
  • Crow, Franklin C.
  • Sewall, Jeffrey R.
출원인 / 주소
  • NVIDIA CORPORATION
인용정보 피인용 횟수 : 0  인용 특허 : 268

초록

Techniques for handling an interrupt in the rasterizer, in accordance with embodiment of the present technology, start with rasterizing one or more primitives of a first context. If an interrupt is received, the tile count of tiles of a current primitive that have been coarse rasterized is saved in

대표청구항

1. A method of handling an interrupt in a rasterizer comprising: starting coarse rasterization of a current primitive of a first process to determine which pixels of a display screen are related to the current primitive;determining, during coarse rasterization of the current primitive, if an interru

이 특허에 인용된 특허 (268)

  1. Chiang Paul ; Ng Pius ; Look Paul, Accelerated multimedia processor.
  2. Clegg, Christopher Michael; Grisenthwaite, Richard Roy, Accessing data values in a cache.
  3. Thrasher, Thomas L, Active pixel determination for line generation in regionalized rasterizer displays.
  4. Lee Chong U. (San Diego CA), Adaptive block size image compression method and system.
  5. Hsieh Minjhing (San Jose CA) Hutchins Edward P. (San Jose CA), Advanced asyncronous video architecture.
  6. Baldwin, David Robert, Antialias mask generation.
  7. Foran James L. ; Leather Mark M., Antialiased imaging with improved pixel supersampling.
  8. MacInnis, Alexander G.; Tang, Chengfuh Jeffrey; Xie, Xiaodong; Patterson, James T.; Kranawetter, Greg A., Apparatus and method for blending graphics and video surfaces.
  9. Duluk, Jr., Jerome F.; Trivedi, Sushma S.; Ng, Sam; Fung, Lindy; Hessel, Richard E.; Benkual, Jack, Apparatus and method for fragment operations in a 3D-graphics pipeline.
  10. Harrell Chandlee B. (Mountain View CA), Apparatus and method for handling data transfer between a general purpose computer and a cooperating processor.
  11. Ahmed, Ashraf; Filippo, Michael A.; Pickett, James K., Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor.
  12. Mahalingaiah Rupaka ; Miller Paul K., Apparatus and method for microcode patching for generating a next address.
  13. Fung Hei Tao, Apparatus and method for synchronizing audio and video frames in an MPEG presentation system.
  14. Paltashev,Timour; Prokopenko,Boris, Apparatus for compressing data in a bit stream or bit pattern.
  15. Assarpour Hamid (Harvard MA) Walton Lea (Shrewsbury MA), Apparatus for exchanging pixel data among pixel processors.
  16. Leasure, Terry Lee; Lattimore, George Mcneil; Ross, Jr., Robert Anthony; Yeung, Gus Wai Yan, Apparatus for unaligned cache reads and methods therefor.
  17. Crow,Franklin C.; Montrym,John S.; Craighead,Matthew J., Apparatus, system, and method for gamma correction of smoothed primitives.
  18. Poulton John W. (Chapel Hill NC) Molnar Steven E. (Chapel Hill NC) Eyles John G. (Chapel Hill NC), Architecture and apparatus for image generation.
  19. Genusov Alexander (Haifa ILX) Friedlander Ram B. (Haifa PA ILX) Feldman Peter (Pittsburg PA) Fruchter Vlad (Haifa ILX) Jaliff Ricardo (Haifa CA ILX) Mohr Asaf (Cupertino CA) Retter Rafi (Haifa ILX), Architecture for integrated concurrent vector signal processor.
  20. Priem Curtis (Fremont CA) Rosenthal David S. H. (Palo Alto CA), Architecture for providing input/output operations in a computer system.
  21. Kuma Takao (Kawasaki JPX) Sakai Kenichi (Kawasaki JPX), Asymmetric vector multiprocessor composed of a vector unit and a plurality of scalar units each having a different archi.
  22. Hutchins, Edward; Zhu, Ming Benjamin; Gupta, Sanjay O.; Heeschen, Scott C.; Garlick, Benjamin J., Binning flush in graphics data processing.
  23. Heng,Pheng Ann; Xie,Yongming; Wong,Tien Tsin; Chui,Yim Pan, Block-based fragment filtration with feasible multi-GPU acceleration for real-time volume rendering on conventional personal computer.
  24. Luick David Arnold, Branch history cache.
  25. Dao Giang H. (Houston TX), Bresenham/DDA line draw circuitry.
  26. Asghar Saf ; Ireton Mark ; Bartkowiak John G., CPU with DSP function preprocessor having look-up table for translating instruction sequences intended to perform DSP fu.
  27. Green Daniel W., Cache circuit with programmable sizing and method of operation.
  28. Colglazier, Daniel J.; Dombrowski, Chris; Genduso, Thomas B., Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency.
  29. Kumar Harsh ; Baweja Gunjeet D. ; Chang Cheng-Feng ; Chan Tim W., Cache memory architecture with on-chip tag array and off-chip data array.
  30. Valko Joseph T. (Pittsburgh PA) Karabin Richard F. (Ruffs Dale PA), Cationic resin containing capped isocyanate groups suitable for use in electrodeposition.
  31. Harney Kevin (Brooklyn NY), Centralized control SIMD processor having different priority levels set for each data transfer request type and successi.
  32. Garlick, Benjamin J.; Hutchins, Edward A., Circuit and method for displaying images using multisamples of non-uniform color resolution.
  33. Minkin, Alexander L.; Rubinstein, Oren, Circuit and method for prefetching data for a texture cache.
  34. Onaya Masato,JPX, Circuit for obtaining an output signal having distributed frequencies around a frequency of an input signal.
  35. Voorhies, Douglas A.; Foskett, Nicholas J.; Papakipos, Matthew N., Clip-less rasterization using line equation-based traversal.
  36. Rohner Michel A. (San Jose CA) Florence Judit K. (Menlo Park CA), Clipping polygon faces through a polyhedron of vision.
  37. Chen Steve S. (Chippewa Falls) Simmons Frederick J. (Neillsville) Spix George A. (Eau Claire) Wilson Jimmie R. (Eau Claire) Miller Edward C. (Eau Claire) Eckert Roger E. (Eau Claire) Beard Douglas R., Cluster architecture for a highly parallel scalar/vector multiprocessor system.
  38. Ruzafa, Santiago Conde; Gil, Ana Martinez; Fernandez, Daniel Ignacio Perez; Martin, Maria Concepcion Perez; Munoz, Francisco Jose Moreno; Jurado, Francisco Wandosell, Compounds and their therapeutic use.
  39. Watkins Gary S. (Salt Lake City UT) Eckart Glen A. (Salt Lake City UT) Brown Russell A. (Salt Lake City UT), Computer graphics priority system with antialiasing.
  40. Hamilton Eric R. (Cupertino CA) Douglas John L. (Santa Cruz CA) Widergren Jeffrey B. (Saratoga CA), Computer-based video compression system.
  41. Tannenbaum David C. (Hurley NY) Schanely Paul M. (Hurley NY) Richardson Leland D. (Kingston NY) Hempel Bruce C. (Tivoli NY), Context management in a graphics system.
  42. Yamasaki, Nobuyuki, Context switching system having context cache and a register file for the save and restore context operation.
  43. Mohamed Moataz A. ; Park Heonchul ; Nguyen Le Trong, Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor.
  44. Kuboki Shigeo (Nakaminato JPX) Sugimoto Norihiko (Katsuta JPX) Inada Shunji (Hitachi JPX) Inada Kazuhisa (Hitachi JPX) Aoki Tomoaki (Ibaraki-ken JPX) Ueno Masahiro (Hitachi JPX) Nakamura Yasushi (Hit, Data communication adapter and data communication terminal apparatus for performing data transmission and reception betw.
  45. Fallon, James J., Data compression systems and methods.
  46. Apperley Norman (Chandlers Ford NY GBX) Edwards Roger J. (Woodstock NY) Foster Raymond L. J. (Landford GBX) Haigh David C. (Winchester GBX) Haslam Michael (Winchester GBX) Verey Peter (Winchester GBX, Data management for plasma display.
  47. Oldfield William H. (Cambridgeshire GBX), Data memories and method for storing multiple categories of data in latches dedicated to particular category.
  48. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX ; Robbins William Philip,GBX, Data pipeline system and data encoding method.
  49. Nagashima, Shigeo; Torii, Shunichi; Omoda, Koichiro; Inagami, Yasuhiro, Data processing system including scalar data processor and vector data processor.
  50. Baker, David; Basoglu, Christopher; Cutler, Benjamin; Gervasio, Gregorio; Lee, Woobin; Mundkur, Yatin; Nojiri, Toru; O'Donnell, John; Poole, legal representative, John; Raman, Ashok; Rehm, Eric; Thekkath, Radhika; Poole, David, Data streamer.
  51. Faanes,Gregory J.; Scott,Steven L.; Lundberg,Eric P.; Moore, Jr.,William T.; Johnson,Timothy J., Decoupled scalar/vector computer architecture system and method.
  52. Duluk, Jr., Jerome F.; Hessel, Richard E.; Arnold, Vaughn T.; Benkual, Jack; Bratt, Joseph P.; Cuan, George; Dodgen, Stephen L.; Fang, Emerson S.; Gong, Zhaoyu; Ho, Thomas Y.; Hsu, Hengwei; Li, Sidon, Deferred shading graphics pipeline processor having advanced features.
  53. Goodman,Christopher J.; Wittenbrink,Craig M.; Hasslen,Robert J.; Ogletree,Thomas M.; Whitman,Scott R., Diamond culling of small primitives.
  54. Ashkenazi Yaron (Haifa ILX), Digital adder and method for adding 64-bit, 16-bit and 8-bit words.
  55. Ellis James P. (Hudson MA) Nangia Era (Marlboro MA) Patwa Nital (Hudson MA) Shah Bhavin (Mountain View CA) Wolrich Gilbert M. (Framingham MA), Digital computer system with cache controller coordinating both vector and scalar operations.
  56. Morton Steven G., Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction.
  57. Toji,Bunpei; Tezuka,Tadanori; Yoshida,Hiroyuki, Display equipment, display method, and recording medium for recording display control program.
  58. Dye Thomas Anthony, Display list processor for operating in processor and coprocessor modes.
  59. Chamdani Joseph I. ; Alford Cecil O., Distributed instruction queue.
  60. Richardson,John J., Driver framework component for synchronizing interactions between a multi-threaded environment and a driver operating in a less-threaded software environment.
  61. Patti Michael F. (Plainsboro NJ) Fedele Nicola J. (Kingston NJ) Harney Kevin (Brooklyn NY) Simon Allen H. (Belle Mead NJ), Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode.
  62. Megory-Cohen Igal (Givat Ela ILX), Dynamic cache partitioning by modified steepest descent.
  63. Hilgendorf Rolf,DEX ; Schwermer Hartmut,DEX ; Soell Werner,DEX, Dynamic conversion between different instruction codes by recombination of instruction elements.
  64. Tzvetkov,Svetoslav D., Early stencil test rejection.
  65. Vignon, Blaise A.; Crow, Franklin C., Edge evaluation techniques for graphics hardware.
  66. Bowhill William J. (Marlborough MA) Dickson Robert (Arlington MA) Durdan W. H. (Waban MA), Efficient protocol for communicating between asychronous devices.
  67. Morgan III,David L.; Sanz Pastor,Ignacio, Efficient use of user-defined shaders to implement graphics operations.
  68. Ireton Mark A., Execute unit configured to selectably interpret an operand as multiple operands or as a single operand.
  69. Lindholm, John Erik; Oberman, Stuart F., Execution of parallel groups of threads with per-instruction serialization.
  70. Hill, David L.; Breuder, Paul D.; Greiner, Robert J.; Bachand, Derek T., External bus transaction scheduling system.
  71. Sweeney Michael A. (Manassas VA), Fast access priority queue for managing multiple messages at a communications node or managing multiple programs in a mu.
  72. Ebrahim Zahir (Mountain View CA) Normoyle Kevin (San Jose CA) Nishtala Satyanarayana (Cupertino CA) Van Loo William C. (Palo Alto CA), Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system.
  73. Barreh,Jama I.; Golla,Robert T., Fetch speculation in a multithreaded processor.
  74. Kilgard,Mark J.; Brown,Patrick R., Floating point buffer system and method for use during programmable fragment processing in a graphics pipeline.
  75. Jouppi Norman P. ; McCormack Joel J., Full-scene antialiasing using improved supersampling techniques.
  76. Porterfield A. Kent, GART and PTES defined by configuration registers.
  77. Crow,Franklin C.; Sewall,Jeffrey R., GPU having raster components configured for using nested boustrophedonic patterns to traverse screen areas.
  78. Cloutier, Laurence, Gamma calibration.
  79. Sutardja, Pantas, Gate capacitor stress reduction in CMOS/BICMOS circuit.
  80. Kawai, Hiroyuki; Streitenberger, Robert; Inoue, Yoshitsugu; Yoshimatsu, Keijiro; Kobara, Junko; Negishi, Hiroyasu, Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel.
  81. Kilgariff,Emmett M.; Bastos,Rui M.; Chen,Wei Chao; Hahn,Douglas J., Graphical shader by using delay.
  82. Dye Thomas Anthony (Austin TX), Graphics accelerator with dual memory controllers.
  83. Parsons, Paul; Baldwin, David Robert, Graphics engine with isochronous context switching.
  84. Duluk, Jr., Jerome F.; Benkual, Jack; Go, Shun Wai; Trivedi, Sushma S.; Hessel, Richard E.; Bratt, Joseph P., Graphics processor with pipeline state storage and retrieval.
  85. Duluk, Jr., Jerome F.; Benkual, Jack; Go, Shun Wai; Trivedi, Sushma S.; Hessel, Richard E.; Bratt, Joseph P., Graphics processor with pipeline state storage and retrieval.
  86. Baldwin David R. (Weybridge GBX) Bigos Andrew (Chertsey GBX), Graphics subsystem with coarse subpixel correction.
  87. Deering, Michael F., Graphics system configured to determine triangle orientation by octant identification and slope comparison.
  88. Deering, Michael F., Graphics system with a variable-resolution sample buffer.
  89. Thayer Larry J. (Ft. Collins CO) Coleman Mark D. (Ft. Collins CO), Graphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile size.
  90. Harrington Steven J. (Holley NY), Halftoning method using space filling curves.
  91. Lentz Derek (Los Gatos CA), Hardware architecture for image generation and manipulation.
  92. Huang,Hsilin, Head/data request in 3D graphics.
  93. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don, High performance cache directory addressing scheme for variable cache sizes utilizing associativity.
  94. Van Hook Timothy J. ; Cheng Howard H. ; DeLaurier Anthony P. ; Gossett Carroll P. ; Moore Robert J. ; Shepard Stephen J. ; Anderson Harold S. ; Princen John ; Doughty Jeffrey C. ; Pooley Nathan F. ; , High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing.
  95. Johnson ; Jr. Lee E. (Round Rock TX) Kokoszka Daryl J. (Austin TX) Larky Steven P. (Austin TX) Sidoli Paolo (Bresso ITX), High performance rasterization engine.
  96. Pfeiffer David M. (Plano TX) Stoner David T. (McKinney TX) Norsworthy John P. (Carrollton TX) Dipert Dwight D. (Richardson TX) Thompson Jay A. (Plano TX) Fontaine James A. (Plano TX) Corry Michael K., High speed image processing system using separate data processor and address generator.
  97. Zurawski John H. (Stow MA) Beach Walter A. (Bedford MA), High speed transfer of instructions from a master to a slave processor.
  98. Mitchell A. Bauman, High-performance modular memory system with crossbar connections.
  99. Landau, Edouard; Sfarti, Adrian; Malamy, Adam; Liu, Mei-Chi; Laker, Robert; Sabella, Paolo, Identifying silhouette edges of objects to apply anti-aliasing.
  100. Inoue Shuji,JPX, Image memory storage system and method for a block oriented image processing system.
  101. Ihara, Yushi; Matsumoto, Yuji; Ishii, Eiichi; Makita, Chizuru; Nojiri, Kohei, Image processing device and method for producing animated image data.
  102. Barton David C. (Vancouver WA), Imposed weight matrix error diffusion halftoning of image data.
  103. Yamazaki,Iwao, Information processing apparatus and software pre-fetch control method.
  104. Van Hook Timothy J. ; Moreton Henry P. ; Fuccio Michael L. ; Pryor ; Jr. Robert W. ; Tuffli ; III Charles F., Instruction methods for performing data formatting while moving data between memory and a vector register file.
  105. John S. Montrym ; Douglas A. Voorhies ; Steven E. Molnar, Integrated graphics processing unit with antialiasing.
  106. Moreton, Henry P.; Legakis, Justin; Rogers, Douglas H., Integrated tessellator in a graphics processing unit.
  107. Crow, Franklin C.; Sewall, Jeffrey R., Interrupt handling techniques in the rasterizer of a GPU.
  108. Huang, Hsilin; Paltashev, Timour; Brothers, John, Interruptible GPU and method for context saving and restoring.
  109. Zelinka, Stephen D.; Praun, Emil C.; Ohazama, Chikai J., Large-scale image processing using mass parallelization techniques.
  110. Talwar,Somit; Markle,David A., Laser scanning apparatus and methods for thermal processing.
  111. Wong Jimmy (Portland OR), Memory arbitration method and apparatus for multiple-cycle memory coprocessors employing a data cache unit and stack RAM.
  112. Harrington Steven J. ; Loce Robert P., Memory efficient method and apparatus to enable tagging of thin antialiased lines.
  113. Anantha, Swaminathan; Pazhyannur, Rajesh S., Method and apparatus for a mobile device to address a private home agent having a public address and a private address.
  114. van Vugt, Henricus Antonius Gerardus, Method and apparatus for antialiased imaging of graphical objects.
  115. Gossett, Carroll Philip; Bosch, Derek; Yen, Shouchern Alex, Method and apparatus for antialiasing by gamma corrected area calculation.
  116. Singh Gurbir ; Wang Wen-Hann ; Rhodehamel Michael W. ; Bauer John M. ; Sarangdhar Nitin V., Method and apparatus for cache memory replacement line identification.
  117. Jouppi,Norman P.; Chang,Chun Fa, Method and apparatus for compositing colors of images using pixel fragments with Z and Z gradient parameters.
  118. Jouppi Norman P. ; McCormack Joel J. ; Chang Chun-Fa, Method and apparatus for compositing colors of images with memory constraints for storing pixel data.
  119. Trivedi,Sushma Shrikant; Bratt,Joseph P.; Benkual,Jack; Arnold,Vaughn Todd; Iwamoto,Derek Fujio, Method and apparatus for data processing.
  120. Koneru, Satyaki; Zaidi, Sajjad A., Method and apparatus for determining bins to be updated for polygons, including lines.
  121. Smith Gerald R. ; Kidd Robert C., Method and apparatus for digital data compression.
  122. Petro Anthony M. ; Blomgren James S., Method and apparatus for dynamic partitionable saturating adder/subtractor.
  123. Hall Michael L. (Marysville WA) Engel Glenn R. (Lake Stevens WA), Method and apparatus for dynamically linking subprogram to main program using tabled procedure name comparison.
  124. Hussain Zahid S., Method and apparatus for efficiently switching state in a graphics pipeline.
  125. Rogers Philip J., Method and apparatus for formatting a texture in a frame buffer.
  126. Wong Daniel Wai-him,CAX ; Aleksic Milovoje M.,CAX, Method and apparatus for generating sub pixel masks in a three dimensional graphic processing system.
  127. Zatz, Harold Robert Feldman; Tannenbaum, David C., Method and apparatus for generation of programmable shader configuration information from state-based control information and program instructions.
  128. Winner Stephanie L. ; Kelley Michael W., Method and apparatus for high performance antialiasing which minimizes per pixel storage and object data bandwidth.
  129. Fowler,Mark C.; Olson,Kevin M., Method and apparatus for high speed block mode triangle rendering.
  130. Leather,Mark M.; Drebin,Robert A.; Van Hook,Timothy J., Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system.
  131. Leather,Mark M.; Drebin,Robert A.; Van Hook,Timothy J., Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system.
  132. Wilde Daniel P., Method and apparatus for internally caching the minimum and maximum XY pixel address values in a graphics subsystem.
  133. Allen, Roger L.; Feldman Zatz, Harold Robert, Method and apparatus for loop and branch instructions in a programmable graphics pipeline.
  134. Sturges Jay J., Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory contro.
  135. Van Dyke, James M.; Margeson, III, James E., Method and apparatus for managing and accessing depth data in a computer graphics system.
  136. Edward Colton Greene ; Patrick Matthew Hanrahan, Method and apparatus for occlusion culling in graphics systems.
  137. Azevedo,Michael Joseph; Walls,Andrew Dale, Method and apparatus for optimizing cache hit ratio in non L1 caches.
  138. Mills Karl Scott ; Holmes Jeffrey Michael ; Bonnelycke Mark Emil ; Owen Richard Charles Andrew, Method and apparatus for optimizing pixel data write operations to a tile based frame buffer.
  139. Floyd, Michael Stephen; Kahle, James Allan; Le, Hung Qui; Moore, John Anthony; Reick, Kevin Franklin; Silha, Edward John, Method and apparatus for patching problematic instructions in a microprocessor using software interrupts.
  140. Ronald D. Larson, Method and apparatus for performing scan conversion in a computer graphics display system.
  141. Alben, Jonah; Ma, Dennis Kd; Kelleher, Brian, Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle.
  142. Aleksic Milivoje M.,CAX ; Wong Daniel Wai-him,CAX, Method and apparatus for processing fragment pixel information in a three-dimensional graphics processing system.
  143. Omtzigt E. Theodore L., Method and apparatus for providing frame-time feedback to graphics application programs.
  144. Atallah Deif ; Kahn Mitchell, Method and apparatus for quickly modifying cache state.
  145. Leather,Mark M., Method and apparatus for rasterizer interpolation.
  146. Hussain, Zahid S.; Millet, Timothy J., Method and apparatus for rasterizing in a hierarchical tile order.
  147. Kuchkuda Roman ; Rigg John ; Enriquez Manuel Rey ; Henson James V. ; Stehley Curt, Method and apparatus for rendering of fractional pixel lists for anti-aliasing and transparency.
  148. John A. Wickeraad ; Stephen B. Lyle ; Brendan A. Voge, Method and apparatus for replacing cache lines in a cache memory.
  149. Mantor, Michael; Mang, Michael Andrew, Method and apparatus for shared microcode in a multi-thread computation engine.
  150. Duluk ; Jr. Jerome F., Method and apparatus for span and subspan sorting rendering system.
  151. Ault, David Nolan; Brown, Patrick Richard; Nadon, Mark Anthony; Tiernan, William Bryan, Method and apparatus for storing and accessing texture maps.
  152. Iourcha, Konstantine; Prokopenko, Boris; Paltashev, Timour; Gladding, Derek, Method and apparatus for triangle rasterization with clipping and wire-frame mode support.
  153. Morein Stephen L. ; Rogers Philip John, Method and apparatus for video graphics antialiasing.
  154. Johns, Charles Ray; Kuo, Wei, Method and apparatus in a data processing system for an asynchronous context switching mechanism.
  155. Narayanaswami Chandrasekhar, Method and apparatus providing efficient rasterization with data dependent adaptations.
  156. Gossett Carroll Philip, Method and system for efficient context switching in a computer graphics system.
  157. Thomas, Jeff, Method and system for efficiently implementing two sided vertex lighting in hardware.
  158. Kyle Johns, Method and system for managing a display image in compressed and uncompressed blocks.
  159. Wyatt, David A., Method and system for optimally sharing memory between a host processor and graphics processor.
  160. Rouet, Christian; Bastos, Rui; Yue, Lordson, Method and system for patching instructions in a shader for a 3-D graphics pipeline.
  161. Zu, Peter Z., Method and system for pre-loading and executing computer instructions within the cache memory.
  162. Crow, Franklin C.; Montrym, John S., Method and system for rendering polygons having abutting edges.
  163. Johl, Manraj Singh; Steinmetz, Joseph Harold; Wakeley, Matthew Paul, Method and system increasing performance substituting finite state machine control with hardware-implemented data structure manipulation.
  164. Gandhi Bhavan R. ; Smith Craig Michael,JPX ; Sullivan James R. ; Couwenhoven Douglas W. ; Rombola Gregory, Method for adaptively compressing residual digital image data in a DPCM compression system.
  165. Naegle, Nathaniel David; Sweeney, Jr., William E.; Morse, Wayne A., Method for context switching a graphics accelerator comprising multiple rendering pipelines.
  166. Oana Baltaretu ; David L. Dignam ; Sanjay O. Gupta, Method for determining tiles in a computer display that are covered by a graphics primitive.
  167. Gossett Carroll Philip ; Goudy Mark ; Bentz Ole, Method for efficient handling of texture cache misses by recirculation.
  168. Douglas A. Voorhies, Method for efficiently rendering color information for a pixel in a computer system.
  169. Emberling,Brian D., Method for improving texture cache access by removing redundant requests.
  170. Furtner, Wolfgang, Method for rasterizing a graphics basic component.
  171. Eichenberger,Alexandre E.; O'Brien,John Kevin Patrick; O'Brien,Kathryn M., Method to efficiently prefetch and batch compiler-assisted software cache accesses.
  172. Lindholm,John Erik; Moy,Simon; Kirk,David B.; Sabella,Paolo E., Method, apparatus and article of manufacture for a transform module in a graphics processor.
  173. Voorhies, Douglas A.; Foskett, Nicholas J., Method, apparatus and article of manufacture for area rasterization using sense points.
  174. Reader Cliff ; Son Jae Cheol ; Qureshi Amjad ; Nguyen Le ; Frederiksen Mark ; Lu Tim, Methods and apparatus for processing video data.
  175. Hux,William A.; Junkins,Stephen, Methods, systems, and data structures for generating a rasterizer.
  176. Kevin J. McGrath ; James K. Pickett, Microcode patch device and method for patching microcode using match registers and patch routines.
  177. Goddard Michael D. ; Christie David S., Microcode patching apparatus and method.
  178. Shiell Jonathan H. ; Bosshart Patrick W., Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure.
  179. Greene, Edward C.; Voorhies, Douglas A.; Sabella, Paolo; Danskin, John M.; Van Dyke, James M., Modified method and apparatus for improved occlusion culling in graphics systems.
  180. Dei, Hiroaki; Hatabu, Atsushi; Ozawa, Kazunori, Moving picture data code conversion/transmission method and device, code conversion/reception method and device.
  181. Reed Tidwell ; Gary Pimentel, Multi-level cache controller.
  182. Dummermuth Ernst, Multi-tasking operation system for industrial controller.
  183. Hagersten Erik E., Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a fi.
  184. Yoshida Toyohiko (Itami JPX), Multiprocessor including system for pipeline processing of multi-functional instructions.
  185. Nemawarkar, Shashank, Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread.
  186. Martell Robert W., Non-clocked early read for back-to-back scheduling of instructions.
  187. Larson Michael K., Non-sequential fetch and store of XY pixel data in a graphics processor.
  188. Chung-Yen Lu TW; Ming-Hao Liao TW, Non-stalling pipeline tag controller.
  189. Yue,Lordson L.; Battle,James T., Optimal initial rasterization starting point.
  190. Bakalash, Reuven; Leviathan, Yaniv, PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications.
  191. McCabe,Daniel H., Parallel architecture for graphics primitive decomposition.
  192. Gooding David N. (Endicott NY) Shimp Everett M. (Endwell NY), Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and locati.
  193. Wasserman, Michael A.; Ing, Elena M.; Nhan, Vannessa M.; Ramani, Nandini; Chang, Charles P., Parallel initialization path for rasterization engine.
  194. Leather, Mark M.; Demers, Eric, Parallel pipeline graphics system.
  195. Ohki Mitsuharu (Tokyo JPX) Yamazaki Takao (Kanagawa JPX) Kurokawa Masuyoshi (Kanagawa JPX) Hashiguchi Akihiko (Kanagawa JPX), Parallel processor apparatus having means for processing signals of different lengths.
  196. Cornett Kevin B. (Wappingers Falls NY) Mark Edward F. (Poughkeepsie NY), Pick correlation.
  197. Ang Michael ; Jacobs Eino, Planar cache layout and instruction stream therefor.
  198. Molnar,Steven E.; French,Mark J.; Montrym,John S.; Schneider,Bengt Olaf; Wilde,Daniel P., Planar z representation for z compression.
  199. Lentz Derek J. (Los Gatos CA) Kosmal David R. (Newark CA) Poole Glenn C. (Fremont CA), Polygon rasterization.
  200. Kang,Inyup; Ethirajan,Karthikeyan, Power collapse for a wireless terminal.
  201. Kim,Hyeong Seog, Power management method and apparatus of wireless local area network module in computer system.
  202. David L Hill ; Derek T. Bachand, Prioritized bus request scheduling mechanism for processing devices.
  203. Hill,David L.; Bachand,Derek T., Prioritized bus request scheduling mechanism for processing devices.
  204. Cota-Robles, Erik, Priority based simultaneous multi-threading.
  205. Diard, Franck R.; Iwamoto, Rick M., Private addressing in a multi-processor graphics processing system.
  206. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  207. Ohtani Akihiko (Moriguchi JPX) Araki Toshiyuki (Takatsuki JPX) Aono Kunitoshi (Hirakata JPX) Akiyama Toshihide (Takatsuki JPX), Program controlled processor wherein vector distributor and vector coupler operate independently of sequencer.
  208. Vartti,Kelvin S.; Weber,Ross M.; Bauman,Mitchell A., Programmable system and method for accessing a shared memory.
  209. Ramani, Nandini; Kehlet, David C.; Kubalska, Ewa M.; Lavelle, Michael G.; Wasserman, Michael A.; Tang, Kevin; Tang, Yan Yan, Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization.
  210. Horsley Brian (Monmouth Junction NJ), Real-time rasterization system for a column-oriented printing apparatus or the like.
  211. Baldwin David Robert,GBX, Rendering architecture with selectable processing of multi-pixel spans.
  212. Nelson, Scott R.; Deering, Michael F.; Ramani, Nandini; Tian, Mark; Shehane, Patrick; Tang, Kevin, Rendering lines with sample weighting.
  213. Zhu, Ming Benjamin, Rendering pipeline.
  214. Zhu,Ming B., Rendering pipeline.
  215. Wong Daniel Wai-him,CAX ; Aleksic Milivoje M.,CAX, Rendering polygons.
  216. Makineni Sivakumar ; Kimn Sunnhyuk ; Doshi Gautam B. ; Golliver Roger A., Scalar hardware for performing SIMD operations.
  217. Beard Douglas R. (Eleva WI) Phelps Andrew E. (Eau Claire WI) Woodmansee Michael A. (Eau Claire WI) Blewett Richard G. (Altoona WI) Lohman Jeffrey A. (Eau Claire WI) Silbey Alexander A. (Eau Claire WI, Scalar/vector processor.
  218. Stokes ; Richard Arthur ; Kuck ; David Jerome ; Jensen ; Carl Anton, Scientific processor.
  219. Leather,Mark M., Selectable multi-performance configuration.
  220. Bastos,Rui M.; Donovan,Walter E., Shader pixel storage in a graphics memory.
  221. Fenney, Simon, Shading 3-dimensional computer generated images.
  222. Redshaw, Jonathan; Morphet, Steve, Shading 3-dimensional computer generated images.
  223. Shiell Jonathan H. ; Chen Ian, Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microi.
  224. Meyers Steven D. (Hurley NY) Ngo Hung C. (Kingston NY) Schwartz Paul R. (Kingston NY), Single register arbiter circuit.
  225. Cohen Earl T. ; Pattin Jay C., Slave cache having sub-line valid bits updated by a master cache.
  226. Moll,Laurent R.; Cheng,Yu Qing; Glaskowsky,Peter N.; Song,Seungyoon Peter, Small and power-efficient cache that can provide data for background DNA devices while the processor is in a low-power state.
  227. Hahn Woo Jong,KRX ; Park Kyong,KRX ; Yoon Suk Han,KRX, Structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors.
  228. Witt David B. ; Hattangadi Rajiv M., Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle.
  229. Fu, Chih-Hong; Ling, I-Chung; Hsu, Huai-Shih, Synchronized two-level graphics processing cache.
  230. Bauman, Mitchell A.; Bloom, Douglas H., System and method for accelerating ownership within a directory-based memory system.
  231. Baker Nick ; Malamy Adam ; Sfarti Adrian ; Paternoster Paul ; Parthasarathy Padma, System and method for adjusting pixel parameters by subpixel positioning.
  232. Brown, John M.; Dyer, Don W.; Mehrotra, Gautam; Lang, Carol L., System and method for assessing performance optimizations in a graphics system.
  233. Kelleher Brian M. (Palo Alto CA), System and method for drawing antialiased polygons.
  234. Senter Cheryl D. ; Wang Johannes, System and method for handling load and/or store operators in a superscalar microprocessor.
  235. Parenteau, Alexandre S.; Lau, Cynthia W., System and method for implementing graphics processing unit shader programs using snippets.
  236. Akeley Kurt Barton ; Gossett Carroll Philip, System and method for merging pixel fragments based on depth range values.
  237. Andrews, Jeffrey A.; Baker, Nicholas R.; Goossen, J. Andrew; Abrash, Michael, System and method for parallel execution of data generation tasks.
  238. Lavelle, Michael G.; Kubalska, Ewa M.; Tang, Yan Yan, System and method for prefetching data from a frame buffer.
  239. Nally Robert Marshall ; Schafer John Charles, System and method for processing multiple received signal sources.
  240. McCormack, Joel James; Farkas, Keith Istvan; Jouppi, Norman P.; Seiler, Larry Dean; McNamara, Robert Stephen, System and method for producing an antialiased image using a merge buffer.
  241. Curb Lisa A. (Round Rock TX) Narayanaswami Chandrasekhar (Austin TX) Saha Avijit (Austin TX), System and method for producing anti-aliased lines.
  242. Howard D Stroyan, System and method for reducing the effects of aliasing in a computer graphics system.
  243. Gossett Carroll Philip, System and method for rendering an image.
  244. Levine Marshall P., System and method of drawing anti-aliased lines using a modified bresenham line-drawing algorithm.
  245. Jenkins Barry, System and method of perception-based image generation and encoding.
  246. Stager Gary B. (Plano TX), System for accessing distributed memory by breaking each accepted access request into series of instructions by using se.
  247. DeAguiar John R. (Sebastopol CA) Larkin Ross M. (Rollings Hills CA), System for managing tiled images using multiple resolutions.
  248. Blumer Marc ; Ando Wayne, System for transferring input/output data independently through an input/output bus interface in response to programmab.
  249. Van Dyke, James M.; Voorhies, Douglas A.; Margeson, III, James E.; Montrym, John, System, method and article of manufacture for an interlock module in a computer graphics processing pipeline.
  250. Haas Jurgen,DEX ; Narayanaswami Chandra ; Schneider Bengt-Olaf, Systems and methods for caching depth information of three-dimensional images.
  251. Schenk,Eric; Lalonde,Paul, Systems and methods for implementing shader-driven compilation of rendering assets.
  252. Boland, Michele B.; Boyd, Charles N.; Kancherla, Anantha R., Systems and methods for providing intermediate targets in a graphics system.
  253. Ostiguy, Jean-Jacques; Paquette, Jean-Francois; Bouchard, Alain, Systems for and methods of context switching in a graphics processing system.
  254. Sutton Neil,CAX, Tamper-resistant surface mounted raceway cover.
  255. Ketan K. Dalal ; Colin D. McCartney, Texture tessellation for three-dimensional models.
  256. Morgan Thomas Schramm ; Jay S. Gondek, Tone dependent plane dependent error diffusion halftoning.
  257. Kim Thomas Dongsuk ; Hawthorne Seth Gordon ; Kosinski Joseph Stanley, Tool and method for diagnosing and correcting errors in a computer program.
  258. Morelli, Daniel J.; Trompower, Michael L., Transceiver control with sleep mode operation.
  259. Guttag Karl M. (Sugar Land TX) Read Christopher J. (Houston TX) Poland Sydney W. (Katy TX) Gove Robert J. (Plano TX) Golston Jeremiah E. (Sugar Land TX), Transfer processor with transparency.
  260. Nielsen Michael J. K. ; Hussain Zahid S., Unified memory computer architecture with dynamic graphics memory allocation.
  261. Aronson, David F.; Patel, Amar; Kancheria, Anantha R.; Gosalia, Anuj B.; Peeper, Craig; Baker, Daniel K.; Tarassov, Iouri; McQuade, Loren, Usage semantics.
  262. Terada Koichi,JPX ; Kojima Keiji,JPX ; Fujikawa Yoshifumi,JPX ; Nojiri Tohru,JPX ; Nishioka Kiyokazu,JPX, VLIW system with predicated instruction execution for individual instruction fields.
  263. Gregory J. Faanes ; Eric P. Lundberg, Vector and scalar data cache for a vector multiprocessor.
  264. William N. Joy ; Marc Tremblay ; Gary Lauterbach ; Joseph I. Chamdani, Vertically and horizontally threaded processor with multidimensional storage for storing thread data.
  265. Bianchini, Jr.,Ronald P., Very wide memory TDM switching system.
  266. Valmiki, Ramanujan K.; Bhatia, Sandeep, Video and graphics system with a video transport processor.
  267. Zhang Tai Y. (Berkeley CA), Video compression using an iterative error data coding method.
  268. Alexander,Gregory W.; Levitan,David S.; Sinharoy,Balaram; Starke,William J., Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache.
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