Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation
Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.
대표청구항▼
1. A method, comprising: performing, via at least one processor, an initial compile comprising: interpreting a high level program;generating a hardware definition comprising a kernel implementable on programmable logic of an integrated circuit (IC) based at least in part upon the high level program,
1. A method, comprising: performing, via at least one processor, an initial compile comprising: interpreting a high level program;generating a hardware definition comprising a kernel implementable on programmable logic of an integrated circuit (IC) based at least in part upon the high level program, by:using a first set of instructions that define new functional units to: determine a first one or more functional units useful for implementing the high level program;determine a second one or more functional units that are not needed to implement the high level program, but that may be useful for implementing subsequent modifications to the high level program; anddefine the hardware definition to include the first one or more functional units and the second one or more functional units; andgenerate a host program comprising machine-readable implementation instructions for a control unit based upon the high level program;using a second set of instructions that do not define new functional units to: interpret the modifications to the high level program; andperform a subsequent compile comprising modifying the machine-readable implementation instructions based upon the modifications, wherein the modified machine-readable implementation instructions make use of at least one of the second one or more functional units;wherein the second one or more functional units of the hardware definition is determined based at least in part upon a throughput measurement of the hardware definition, a goal of reducing initial compiles, or a combination thereof. 2. The method of claim 1, comprising running a compiler to perform the initial compile and a programmable logic design software to perform the subsequent compile. 3. The method of claim 2, adjusting, via the compiler, a number of the second one or more functional units in the hardware definition based upon an amount of programmable logic area needed to implement the hardware definition, flexibility of the hardware definition to handle modifications to the host program, or a combination thereof. 4. The method of claim 2, comprising determining, via the compiler, a number of the second one or more functional units in the hardware definition based upon a balancing of a tradeoff between an amount of programmable logic area needed to implement the hardware definition and a throughput measurement of the hardware definition. 5. The method of claim 4, balancing, via the compiler, the tradeoff by utilizing the formula: a number of cycles used to execute each thread/(an area consumed by the programmable logic*a number of parallel threads). 6. The method of claim 1, comprising: determining, via the compiler, a critical path of the host program; and copying, via the compiler, a kernel on the critical path to increase throughput. 7. The method of claim 6, comprising determining, via the compiler, the critical path by: determining a set of kernels called by the host program;estimating a data path for each kernel in the set of kernels;determining an execution time of each kernel; summing the execution time of each kernel along an execution path of the host program to determine a path with the largest execution time. 8. The method of claim 1, comprising implement, via the compiler, a second kernel using unused functional units of the kernel generated by the initial compile. 9. The method of claim 1, comprising: determining, via the compiler, unused functional units in two or more kernels, andimplementing, via the compiler, a new kernel using at least a portion of the unused functional units in the two or more kernels. 10. The method of claim 1, comprising: receiving, via the compiler, compiler flexibility information from a programmable logic designer; andgenerating, via the compiler, the hardware definition based upon the compiler flexibility information. 11. The method of claim 10, comprising receiving a target vertical market for the high level program and generating the hardware definition based at least in part upon the high level program. 12. The method of claim 11, wherein the target vertical market comprises a financial services market and the at least one computer is configured to generate the hardware definition with trigonometry functional units, floating point functional units, or a combination thereof based upon the financial services market. 13. The method of claim 10, wherein the compiler flexibility information comprises an indication of a preference in tradeoff between increased throughput or a reduction in a number of subsequent initial builds. 14. The method of claim 13, comprising: adding a programmable kernel when the preference is the reduction in a number of subsequent initial builds andadding a non-programmable hardware pipeline when the preference is the increase in throughput. 15. A system, comprising: a compiler configured to: interpret a high level program comprising machine-readable instructions representative of high-level functionality to be implemented on an integrated circuit (IC); andperform an initial compile configured to define and generate a hardware definition comprising one or more kernels implementable on the IC based at least in part on the high level program, wherein the one or more kernels comprise: a first one or more functional units useful for implementing the high level program; anda second one or more functional units that are not needed to implement the high level program, but may be useful to implement one or more changes to the high level program; anda programmable logic design software configured to: detect the one or more changes to the high-level program; andperform a subsequent compile configured to implement the one or more changes utilizing the second one or more functional units of the hardware definition without modifying the hardware definition;wherein the compiler is configured to define the second one or more functional units and generate the hardware definition based at least in part upon balancing a tradeoff between at least two of: an amount of programmable logic area utilized for the hardware definition, a throughput measurement of the hardware definition, and a likelihood that additional initial compiles will be needed based upon future changes to the high-level program. 16. The system of claim 15, wherein the programmable logic design software is configured to partition the one or more kernels into a first partition and a second partition, wherein a second initial compile or a second subsequent compile may be performed on the one or more kernels in either the first partition or the second partition without affecting the kernels in alternative partition. 17. A tangible, non-transitory, computer-readable medium, comprising: a first set of machine-readable instructions that define new functional units to: interpret a high level program comprising machine-readable instructions representative of high-level functionality to be implemented on an integrated circuit (IC); andperform an initial compile configured to define and generate a hardware definition comprising a kernel implementable on the IC based at least in part on the high level program, wherein the kernel comprises a first one or more functional units to implement the high level program and a second one or more functional units not needed to implement the high-level program, but that may be useful to implement one or more changes to the high-level program;detect the one or more changes to the high-level program; anda second set of machine-readable instructions that do not define new functional units to: perform a subsequent compile configured to implement the one or more changes utilizing at least one of second one or more functional units of the hardware definition without modifying the hardware definition;size the hardware definition based upon balancing a tradeoff between an amount of programmable logic area utilized for the hardware definition and a likelihood that additional initial compiles will be needed based upon future changes to the high-level program, by: duplicating at least a portion of a kernel of a system to increase throughput,modifying a programmable hardware definition into a non-programmable hardware pipeline to increase efficiency of the hardware definition, obtaining compiler flexibility information from a programmable logic designer and defining the hardware definition based upon the compiler flexibility information, or a combination thereof. 18. The tangible, non-transitory, computer-readable medium of claim 17, wherein the size of the hardware definition is controlled by the compiler through modifying a number of functional units in the hardware definition. 19. The tangible, non-transitory, computer-readable medium of claim 17, wherein the compiler is configured to duplicate at least one kernel on a critical path of a programmable logic implementation to increase throughput. 20. The tangible, non-transitory, computer-readable medium of claim 17, wherein the compiler flexibility information comprises: an indication to: generate a non-programmable hardware pipeline for a kernel,partition one or more kernels into a partition,alleviate a number of initial compiles,reduce an amount of programmable logic area needed for the hardware definition, or a combination thereof;wherein the system is configured to:partition one or more kernels into partitions when there is an indication to partition one or more kernels into a partition,increase a number of functional units in the kernel when there is an indication to alleviate the number of initial compiles, anddecrease a number of functional units in the kernel when there is an indication to reduce an amount of programmable logic area needed for the hardware definition.
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이 특허에 인용된 특허 (3)
Tse, John; Carvalho, Neville, Method and apparatus for circuit block reconfiguration EDA.
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