Electronic device for protecting against a polarity reversal of a DC power supply voltage, and its application to motor vehicles
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02H-003/18
H01L-027/02
H01L-027/088
H02H-011/00
출원번호
US-0041654
(2013-09-30)
등록번호
US-9142951
(2015-09-22)
우선권정보
FR-09 55273 (2009-07-28)
발명자
/ 주소
Pavlin, Antoine
출원인 / 주소
STMicroelectronics (Rousset) SAS
대리인 / 주소
Slater & Matsil, L.L.P.
인용정보
피인용 횟수 :
0인용 특허 :
19
초록▼
Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output ter
Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output terminal, a command circuit configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and a control circuit configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions.
대표청구항▼
1. A device comprising: an input having a first input terminal configured to receive an expected positive polarity of an input DC power supply voltage;an output having a first output terminal configured to deliver the positive polarity of an output DC power supply voltage; anda protection circuit co
1. A device comprising: an input having a first input terminal configured to receive an expected positive polarity of an input DC power supply voltage;an output having a first output terminal configured to deliver the positive polarity of an output DC power supply voltage; anda protection circuit coupled between the input and the output configured to protect the output against a polarity reversal at the input of the input DC power supply voltage, the protection circuit having integrated components comprising: an N-channel main transistor having a source coupled to the first input terminal and a drain coupled to the first output terminal;a command circuit configured to render the main transistor blocked in an event of a polarity reversal at the input and further configured to otherwise render the main transistor conducting by maintaining a gate of the main transistor at a first voltage; anda control circuit configured to dynamically adjust a bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor during at least the polarity reversal at the input and according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions;wherein the control circuit comprises a first control transistor having a substrate region connected to its source, the drain of which is connected to the source of the main transistor and the gate of which is connected to the drain of the main transistor. 2. The device according to claim 1, wherein the substrate regions of the components are produced within semiconductive regions having a conductivity opposite to that of the substrate regions, the semiconductive regions being connected either to the first output terminal or to ground depending on the type of conductivity of these semiconductive regions. 3. The device according to claim 2, wherein the substrate regions of the components are of P-conductivity type formed in semiconductive regions of N-conductivity type connected to the first output terminal, and the control circuit is configured to link the P-conductivity type substrate regions to the source of the main transistor if the source voltage is less than the drain voltage or to the drain of the main transistor if the source voltage is greater than the drain voltage. 4. The device according to claim 2, wherein the control circuit comprises a comparator having two inputs respectively connected to the source and to the drain of the main transistor, and a multiplexer having an input connected to the substrate regions, two outputs respectively connected to the source and to the drain of the main transistor, and a command input connected to the output of the comparator. 5. The device according to claim 2, wherein the control circuit further comprises a second control transistor configured to be conducting, having its source connected to the drain of the main transistor, its substrate region connected to its drain and to the substrate region of the first control transistor and its gate connected to its drain, the drain of the second control transistor being connected to the source of the first control transistor, the substrate regions of the components being connected to the substrate regions of the first and second control transistors which themselves form part of the components. 6. The device according to claim 1, wherein the command circuit comprises a charge pump, the output of which is connected to the gate of the main transistor. 7. The device according to claim 6, wherein the command circuit further comprises a voltage regulation circuit connected to the first output terminal and powering the charge pump. 8. A polarity reversal protection circuit comprising: an input terminal and an output terminal;a main transistor coupled between the input terminal and the output terminal;a command circuit connected between the input terminal and the output terminal and configured to solely control a voltage of a gate of the main transistor and render the main transistor blocked in response to a polarity reversal at the input terminal and further configured to render the main transistor conducting otherwise; anda control circuit configured to dynamically adjust a bias of substrate regions of components connected to the main transistor by connecting the substrate regions either to a source or to a drain of the main transistor, wherein the control circuit comprises a first control transistor and a second control transistor, wherein the second control transistor is configured to be conducting and has its source connected to the drain of the main transistor, and its substrate region and gate connected to its drain and to a substrate region of the first control transistor, and wherein the drain of the second control transistor is connected to the source of the first control transistor. 9. The polarity reversal protection circuit of claim 8, wherein the main transistor is an N-channel transistor having a source coupled to the input terminal and further having a drain coupled to the output terminal. 10. The polarity reversal protection circuit of claim 8, wherein the control circuit is further configured to bias the substrate regions by connecting the substrate regions to a source or to a drain of the main transistor according to at least one of a value of a voltage present at a source of the main transistor, a value of a voltage present at a drain of the main transistor, and a conductivity type of the substrate regions. 11. The polarity reversal protection circuit of claim 8, wherein the components connected to the main transistor are active devices in the control circuit. 12. The polarity reversal protection circuit of claim 11, wherein the substrate regions of the components are of P-conductivity type formed in semiconductor regions of N-conductivity type connected to the output terminal, and the control circuit is configured to link the P-conductivity type substrate regions to a source of the main transistor when a source voltage is less than a drain voltage and to link the P-conductivity type substrate regions to a drain of the main transistor when the source voltage is greater than the drain voltage. 13. The polarity reversal protection circuit of claim 8, the control circuit having a multiplexer having a first input connected to the substrate regions, two first outputs respectively connected to a source and to a drain of the main transistor, and a command input, wherein the multiplexer connects the first input to one of the two first outputs based on a signal at the command input. 14. The polarity reversal protection circuit of claim 13, the control circuit comprising a comparator having a second output connected to the command input of the multiplexer and further having second inputs connected to a source and to a drain of the main transistor, the comparator transmitting a signal to the command input based on a voltage difference between the second inputs. 15. The polarity reversal protection circuit of claim 8, wherein the command circuit comprises a charge pump having an output connected to a gate of the main transistor, the charge pump providing to the gate a first voltage greater than a second voltage at the input terminal in normal operating mode. 16. The polarity reversal protection circuit of claim 15, wherein the charge pump maintains the main transistor in an “on” state during operation of the charge pump, and wherein the main transistor is in an “off” state during non-operation of the charge pump. 17. The polarity reversal protection circuit of claim 16, wherein the command circuit comprises a voltage regulation circuit connected between the output terminal and ground, the voltage regulation circuit powering the charge pump when the voltage between the output terminal and ground exceeds a predetermined operating voltage, the voltage regulation circuit stopping power to the charge pump when the voltage between the output terminal and ground falls below a predetermined operating voltage. 18. The polarity reversal protection circuit of claim 8, wherein the main transistor, the protection circuit and the command circuit are formed in a single integrated circuit device. 19. A system comprising: a DC power supply providing a first DC voltage;an electronic unit connected to the DC power supply and powered by the first DC voltage; anda device coupled between the DC power supply and the electronic unit, the device including:a polarity reversal protection circuit disposed between the DC power supply at a first input terminal and the device at a first output terminal, the polarity reversal protection circuit comprising: an N-channel main transistor disposed between the first input terminal and the first output terminal;a command circuit blocking current flow through the N-channel main transistor from the first input terminal to the first output terminal in response to a polarity reversal at the first input terminal and permitting current flow in normal operation by maintaining a gate of the N-channel main transistor at a voltage determined by the command circuit; anda control circuit dynamically adjusting a bias of substrate regions of active components of the command circuit and of the control circuit by connecting the substrate regions to one of the first input terminal and the first output terminal according to voltages at the first input terminal and the first output terminal, wherein the control circuit comprises a first control transistor having a substrate region connected to its source, a drain of which is connected to a source of the N-channel main transistor and a gate of which is connected to a drain of the N-channel main transistor. 20. The system of claim 19, wherein the N-channel main transistor has a source coupled to the first input terminal and a drain coupled to the first output terminal, wherein the command circuit blocks current flow from the first input terminal to the first output terminal by turning off the main transistor. 21. An electronic device for protecting against a polarity reversal of a DC power supply voltage, comprising: an N-channel main transistor mounted on a line of expected positive polarity of the DC power supply voltage; anda command circuit comprising a charge pump circuit, the command circuit associated with a dynamic biasing circuit for biasing substrate regions of active components connected to the main transistor;wherein the main transistor and the command circuit are formed on a single integrated circuit; andwherein the charge pump circuit renders the N-channel main transistor conducting during the expected positive polarity of the DC power supply by maintaining, at a gate of the N-channel main transistor, a gate voltage set by the charge pump; andwherein the charge pump circuit renders the N-channel main transistor blocked during a negative polarity of the DC power supply by the charge pump circuit powering down and causing the potential of the gate to follow a potential of the source of the N-channel main transistor. 22. A polarity reversal protection circuit comprising: an input terminal and an output terminal;a main transistor coupled between the input terminal and the output terminal and having a first substrate biased to a source of the main transistor;a command circuit coupled between a gate of the main transistor and the output terminal; configured to render the main transistor blocked in response to a polarity reversal at the input terminal and further configured to render the main transistor conducting otherwise; anda control circuit having one or more active devices and a multiplexer, the multiplexer having a first output connected to the source of the main transistor and a second output connected to a drain of the main transistor, the multiplexer further having an input connected to a second substrate of the one or more active devices, the control circuit further comprising a first control transistor having a substrate region connected to its source, a drain of which is connected to the source of the main transistor and a gate of which is connected to the drain of the main transistor. 23. A method of protecting a circuit against polarity reversal comprising: connecting a circuit path between an input terminal and an output terminal through a main transistor in a normal operating mode by applying a voltage to a gate of the main transistor with a charge pump in a command circuit;blocking the circuit path, in a reversed polarity mode at the input terminal, by blocking current though the main transistor with the command circuit, the blocking comprising discharging the gate of the main transistor by connecting the gate to the source of the main transistor through a resistive path comprising at least one passive resistor and so that a voltage of the gate of the main transistor follows a voltage of the source of the main transistor during the reversed polarity mode; anddynamically adjusting a bias of at least one active device in a control circuit by connecting a substrate of the at least one active device to a source or a drain of the main transistor. 24. The method of claim 23, wherein a bias of the at least one active device is biased according to a value of voltages present at the source and the drain of the main transistor and a type of conductivity of the substrate.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (19)
Kim, Ju-Young; Jung, Do-Yang; Kim, Do-Youn; Kang, Ju-Hyun, Apparatus for balancing of battery pack having function of prevention of over-discharge.
Williams Richard K. (Cupertino CA), Bidirectional current blocking MOSFET for battery disconnect switching including protection against reverse connected ba.
Pavlin Antoine (Aix En Provence FRX) Sicard Thierry (Fenouillet FRX) Simon Marc (Tournefeuille FRX), Circuit for dynamic isolation of integrated circuits.
Williams Richard K. (Cupertino CA) Toombs Thomas (Los Altos CA) Owyang King (Atherton CA) Yilmaz Hamza (Saratoga CA), Reverse battery protection device containing power MOSFET.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.