Metal oxide layer composition control by atomic layer deposition for thin film transistor
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/786
G09G-003/20
H01L-029/66
H01L-021/8238
H01L-021/02
H01L-029/10
출원번호
US-0750959
(2013-01-25)
등록번호
US-9171960
(2015-10-27)
발명자
/ 주소
Hong, John Hyunchul
Ryang, Hong-Son
Kim, Cheonhong
Fung, Tze-Ching
출원인 / 주소
QUALCOMM MEMS Technologies, Inc.
대리인 / 주소
Weaver Austin Villeneuve & Sampson LLP
인용정보
피인용 횟수 :
0인용 특허 :
5
초록▼
This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semicond
This disclosure provides systems, methods and apparatus for a thin film transistor (TFT) device on a substrate. In one aspect, the TFT device includes a gate electrode, an oxide semiconductor layer, and a gate insulator between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least two metal oxides, with the two metal oxides having a varying concentration relative to one another between a lower surface and an upper surface of the oxide semiconductor layer. The TFT device also includes a source metal adjacent to a portion of the oxide semiconductor layer and a drain metal adjacent to another portion of the oxide semiconductor layer. The composition of the oxide semiconductor layer can be precisely controlled by a sequential deposition technique using atomic layer deposition (ALD).
대표청구항▼
1. A thin film transistor (TFT) device, comprising: a gate;an active layer having a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the active layer includes a plurality of sublayers of a first metal oxide
1. A thin film transistor (TFT) device, comprising: a gate;an active layer having a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the active layer includes a plurality of sublayers of a first metal oxide and a plurality of sublayers of a second metal oxide in a stacked arrangement from a first surface to a second surface of the active layer, wherein the arrangement includes an upper portion and a lower portion, the upper portion having at least one second metal oxide sublayer and a greater number of sublayers of the first metal oxide than the second metal oxide, and the lower portion having at least one first metal oxide sublayer and a greater number of sublayers of the second metal oxide than the first metal oxide;a gate insulator between the active layer and the gate;a source metal adjacent to the source region of the active layer; anda drain metal adjacent to the drain region of the active layer. 2. The TFT device of claim 1, wherein the gate is over the gate insulator and the active layer is below the gate insulator. 3. The TFT device of claim 1, wherein the gate is below the gate insulator and the active layer is over the gate insulator. 4. The TFT device of claim 1, wherein the active layer substantially includes a substantially semiconducting metal oxide proximate the interface between the active layer and the gate insulator. 5. The TFT device of claim 1, wherein the active layer substantially includes a substantially insulating metal oxide proximate a surface of the active layer facing away from the gate. 6. The TFT device of claim 1, wherein the active layer includes indium-gallium-zinc-oxide (IGZO). 7. The TFT device of claim 6, wherein the concentration of gallium oxide increases from a surface of the active layer facing away from the gate to a surface of the active layer facing towards from the gate. 8. The TFT device of claim 7, wherein the concentration of gallium oxide is less than about 5% at the surface of the active layer facing away from the gate and greater than about 95% at the surface of the active layer facing towards the gate. 9. The TFT device of claim 1, wherein the active layer is less than about 100 Å in thickness. 10. The TFT device of claim 1, wherein the active layer is amorphous. 11. The TFT device of claim 1, wherein one of the two metal oxides includes at least one of gallium oxide, aluminum oxide, hafnium oxide, and germanium oxide. 12. The TFT device of claim 1, wherein one of the two metal oxides includes at least one of indium oxide and zinc oxide. 13. The TFT device of claim 1, wherein the active layer is formed on a substrate, and wherein the substrate includes glass or plastic. 14. An apparatus comprising: the TFT device of claim 1;a display;a processor that is configured to communicate with the display, the processor being configured to process image data; anda memory device that is configured to communicate with the processor. 15. The apparatus of claim 14, further comprising: a driver circuit configured to send at least one signal to the TFT device in electrical communication with the display; anda controller configured to send at least a portion of the image data to the driver circuit. 16. The apparatus of claim 14, further comprising: an image source module configured to send the image data to the processor, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter; andan input device configured to receive input data and to communicate the input data to the processor. 17. An apparatus, comprising: a substrate; anda thin film transistor (TFT) over the substrate, the TFT comprising:a gate metal over the substrate;a dielectric layer over the substrate and the gate metal;an oxide semiconductor layer over the dielectric layer, wherein the oxide semiconductor layer has a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the oxide semiconductor layer includes a plurality of sublayers of a first metal oxide and a plurality of sublayers of a second metal oxide in a stacked arrangement from a first surface to a second surface of the active layer, wherein the arrangement includes an upper portion and a lower portion, the upper portion having at least one second metal oxide sublayer and a greater number of sublayers of the first metal oxide than the second metal oxide, and the lower portion having at least one first metal oxide sublayer and a greater number of sublayers of the second metal oxide than the first metal oxide;a source metal adjacent to the source region of the oxide semiconductor layer; anda drain metal adjacent to the drain region of the oxide semiconductor layer. 18. The apparatus of claim 17, wherein the oxide semiconductor layer substantially includes a substantially semiconducting metal oxide proximate the lower surface of the oxide semiconductor layer. 19. The apparatus device of claim 17, wherein the oxide semiconductor layer includes indium-gallium-zinc-oxide (IGZO). 20. The apparatus of claim 17, wherein the oxide semiconductor layer is less than about 100 Å in thickness. 21. An apparatus, comprising: a substrate; anda thin film transistor (TFT) over the substrate, the TFT comprising:an oxide semiconductor layer over the substrate, wherein the oxide semiconductor layer has a source region, a drain region, and a channel region, wherein the channel region is between the source region and the drain region, and wherein the oxide semiconductor layer includes a plurality of sublayers of a first metal oxide and a plurality of sublayers of a second metal oxide in a stacked arrangement from a first surface to a second surface of the oxide semiconductor layer, wherein the arrangement includes an upper portion and a lower portion, the upper portion having at least one second metal oxide sublayer and a greater number of sublayers of the first metal oxide than the second metal oxide, and the lower portion having at least one first metal oxide sublayer and a greater number of sublayers of the second metal oxide than the first metal oxide;a dielectric layer over the channel region of the oxide semiconductor layer;a gate metal over the dielectric layer;a source metal adjacent to the source region of the oxide semiconductor layer; anda drain metal adjacent to the drain region of the oxide semiconductor layer. 22. The apparatus of claim 21, wherein the oxide semiconductor layer substantially includes a substantially semiconducting metal oxide proximate the upper surface of the oxide semiconductor layer. 23. The apparatus device of claim 21, wherein the oxide semiconductor layer includes indium-gallium-zinc-oxide (IGZO). 24. The apparatus of claim 21, wherein the oxide semiconductor layer is less than about 100 Å in thickness.
Zhou, Otto Z.; Oh, Soojin; Zhang, Jian; Cheng, Yuan; Shimoda, Hideo, Methods and apparatus for patterned deposition of nanostructure-containing materials by self-assembly and related articles.
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