A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instru
A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.
대표청구항▼
1. A watchdog monitor system comprising: a timer circuit configured to count a value in synchronization with a clock signal, to output a reset signal to reset a target circuit of the watchdog timer circuit when the counted value reaches a time-out value, and to reset the counted value when the watch
1. A watchdog monitor system comprising: a timer circuit configured to count a value in synchronization with a clock signal, to output a reset signal to reset a target circuit of the watchdog timer circuit when the counted value reaches a time-out value, and to reset the counted value when the watchdog timer circuit receives a timer refresh signal; anda timer control circuit configured to receive multi-bit data in synchronization with the timer refresh signal and to stop the timer circuit from counting the value when the multi-bit data is identical to predetermined multi-bit data,a power integrated circuit (IC) formed on a semiconductor substrate,wherein said power IC further comprises a power supply circuit that generates a predetermined operation power supply voltage in response to receiving an external power supply voltage;a reset circuit that outputs an external reset signal in response to receiving either a power-on reset instruction concerning the power supply voltage being output from said power supply circuit or the reset signal due to time-out of the timer circuit of said watchdog timer circuit;a first external terminal that receives from outside of said power IC a control signal used for the timer refresh signal;a second external terminal that outputs an external reset signal to outside of said power IC;a third external terminal that receives the multi-bit data signal from outside of said power IC;a fourth external terminal that outputs the predetermined operation power supply voltage to the outside of said power IC; anda fifth external terminal that receives other instructions from outside of said power IC. 2. The watchdog timer circuit according to claim 1, wherein said timer control circuit includes a multi-bit shift register that sequentially latches the multi-bit data at a timing of receipt of the timer refresh signal, and a logic gate circuit that inputs the multi-bit data latched by the multi-bit shift register and that determines whether the multi-bit data is identical with the predetermined multi-bit data. 3. The watchdog timer circuit according to claim 1, wherein all bits of the predetermined multi-bit data are not the same value, andwherein the timer control circuit includes a logic gate that outputs the reset signal to reset the target circuit when all bits of the multi-bit data are the same value. 4. A watchdog monitor system comprising: the power IC as recited in claim 1;a microcomputer coupled to the first to fourth external terminals of said power IC; anda switch circuit coupled to the fifth external terminal,wherein said microcomputer outputs the multi-bit data being equal to the predetermined multi-bit data to the third external terminal and the timer refresh signal to the first external terminal when the microcomputer goes into a low power consumption state, andwherein said timer control circuit causes said timer circuit to stop its timer count operation on condition that said switch circuit is in a switch-off state. 5. The watchdog monitor system according to claim 4, wherein said timer control circuit restarts the timer count operation of said timer circuit when said switch circuit changes from the switch-off state to a switch-on state or when the multi-bit data outputted from the microcomputer is not equal to the predetermined multi-bit data. 6. The watchdog monitor system according to claim 5, wherein said microcomputer has the low power consumption state which is either a first low power consumption state in which the feeding of the predetermined operation power supply voltage is stopped or a second low power consumption state in which at least a central processing unit included in the microcomputer is deactivated while retaining the predetermined operation power supply voltage feeding,wherein said microcomputer supplies a sixth external terminal of said power IC with a signal for instruction of stop of feeding of the predetermined operation power supply voltage when going into the first low power consumption state, andwherein said power IC stops outputting of said predetermined operation power supply voltage on condition that the power IC receives the instruction for stopping the feeding of the predetermined operation power supply voltage via said sixth external terminal and the switch circuit is in the switch-off state and restarts outputting of the predetermined operation power supply voltage on condition that the instruction for stopping the feeding of the predetermined operation power supply voltage is deactivated or the switch circuit is in the switch-on state. 7. A watchdog monitor system comprising: the power IC as recited in claim 1;a microcomputer coupled to the first to fourth external terminals of said power IC; anda switch circuit coupled to the fifth external terminal,wherein said power IC further includes a communication interface circuit which is coupled to a network bus through a network-side terminal and which is coupled to said microcomputer via control-side terminals,wherein the control-side terminals include an external communication terminal and an external mode terminal,wherein said outputs the multi-bit data being equal to the predetermined multi-bit data to the third external terminal and the timer refresh signal to the third external terminal when the microcomputer goes into a low power consumption state, andwherein said timer control circuit causes said timer circuit to stop its timer count operation on condition that said switch circuit is in a switch-off state and the communication interface circuit receives a stand-by instruction through the external mode terminal. 8. The watchdog monitor system according to claim 7, wherein said timer control circuit restarts the timer count operation of said timer circuit when said switch circuit changes from the switch-off state to a switch-on state or when said communication interface circuit receives an activation instruction through the external mode terminal or when the multi-bit data outputted from the microcomputer is not equal to the predetermined multi-bit data. 9. The watchdog monitor system according to claim 8, wherein said communication interface circuit is for use with an in-vehicle network,wherein said microcomputer constitutes an electronic control unit (ECU) for use in motor vehicles, andwherein said switch circuit is an ignition switch. 10. The watchdog monitor system according to claim 9, wherein said microcomputer has the low power consumption state which is either a first low power consumption state in which the feeding of the predetermined operation power supply voltage is stopped or a second low power consumption state in which at least a central processing unit included in the microcomputer is deactivated while feeding of the power supply voltage is sustained,wherein said microcomputer supplies a sixth external terminal of said power IC with a signal for instruction of stop of the feeding of the predetermined operation power supply voltage when going into the first low power consumption state, andwherein said power IC stops outputting of said predetermined operation power supply voltage on condition that the power IC receives the instruction for stopping the feeding of the predetermined operation power supply voltage via said sixth external terminal and the switch circuit is in the switch-off state and restarts outputting of the predetermined operation power supply voltage on condition that the instruction for stopping the feeding of the predetermined operation power supply voltage is deactivated or the switch circuit is in the switch-on state. 11. A watchdog monitor system, comprising: a power IC;a microcomputer coupled to said power IC; anda switch circuit coupled to said power IC,wherein said power IC comprises a watchdog timer circuit;a power supply circuit that receives an external power supply voltage and that generates a predetermined operation power supply voltage; anda reset circuit that outputs an external reset signal in response to receipt of either a power-on reset instruction relating to the power supply voltage to be output from said power supply circuit or a reset signal outputted from said watchdog timer circuit,wherein said watchdog timer circuit comprises a timer that counts a value in synchronization with a clock signal, outputs the reset signal when the counted value reaches a time-out value, and resets the counted value when the watchdog timer circuit receives a timer refresh signal; anda timer control circuit that receives multi-bit data in synchronization with the timer refresh signal and that stops the timer circuit from counting the value when the multi-bit data is identical with a predetermined multi-bit data, andwherein said microcomputer outputs the multi-bit data being equal to predetermined multi-bit data and the timer refresh signal to the power IC when the microcomputer goes into a low power consumption state, andwherein said power integrated circuit is formed on a semiconductor substrate,wherein said power IC further comprises a power supply circuit that generates a predetermined operation power supply voltage in response to receiving an external power supply voltage;a reset circuit that outputs an external reset signal in response to receiving either a power-on reset instruction concerning the power supply voltage being output from said power supply circuit or the reset signal due to time-out of the timer circuit of said watchdog timer circuit;a first external terminal that receives from outside of said power IC a control signal used for the timer refresh signal;a second external terminal that outputs an external reset signal to outside of said power IC;a third external terminal that receives the multi-bit data signal from outside of said power IC;a fourth external terminal that outputs the predetermined operation power supply voltage to the outside of said power IC; anda fifth external terminal that receives other instructions from outside of said power IC. 12. The watchdog monitor system according to claim 11, wherein said microcomputer outputs the multi-bit data such that all bits of the multi-bit data are not the same value, andwherein said timer control circuit outputs the reset signal to the reset circuit when the timer control circuit detects that all bits of the multi-bit data are the same value. 13. The watchdog monitor system according to claim 12, wherein said microcomputer is reset in response to receiving the external reset signal outputted from said reset circuit and starts to output the multi-bit data after the reset. 14. A watchdog monitor system, comprising: a power IC;a microcomputer coupled to said power IC; anda switch circuit coupled to said power IC,wherein said power IC comprises a watchdog timer circuit;a power supply circuit that receives an external power supply voltage and that generates a predetermined operation power supply voltage;a reset circuit that outputs an external reset signal in response to receiving either a power-on reset instruction concerning the power supply voltage to be output from said power supply circuit or a reset signal outputted from said watchdog timer circuit; anda communication interface circuit coupled to said microcomputer and to a network bus,wherein said watchdog timer circuit comprises a timer circuit that counts a value in synchronization with a clock signal, outputs the reset signal when the counted value reaches a time-out value, and resets the counted value when the watchdog timer circuit receives a timer refresh signal; anda timer control circuit that receives multi-bit data in synchronization with the timer refresh signal and stops the timer circuit from counting the value when the multi-bit data is identical with a predetermined multi-bit data, the communication interface circuit receives a stand-by instruction, and the switch circuit is in a switch-off state, andwherein said microcomputer outputs the multi-bit data being equal to the predetermined multi-bit data and the timer refresh signal to the power IC when the microcomputer goes into a low power consumption state, andwherein said power integrated circuit is formed on a semiconductor substrate,wherein said power IC further comprises a power supply circuit that generates a predetermined operation power supply voltage in response to receiving an external power supply voltage;a reset circuit that outputs an external reset signal in response to receiving either a power-on reset instruction concerning the power supply voltage being output from said power supply circuit or the reset signal due to time-out of the timer circuit of said watchdog timer circuit;a first external terminal that receives from outside of said power IC a control signal used for the timer refresh signal;a second external terminal that outputs an external reset signal to outside of said power IC;a third external terminal that receives the multi-bit data signal from outside of said power IC;a fourth external terminal that outputs the predetermined operation power supply voltage to the outside of said power IC; anda fifth external terminal that receives other instructions from outside of said power IC. 15. The watchdog monitor system according to claim 14, wherein said microcomputer outputs the multi-bit data such that all bits of the multi-bit data are not the same value, andwherein said timer control circuit outputs the reset signal to the reset circuit when the timer control circuit detects that all bits of the multi-bit data are the same value. 16. The watchdog monitor system according to claim 15, wherein said microcomputer is reset in response to receipt of the external reset signal outputted from said reset circuit and starts to output the multi-bit data after the reset.
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이 특허에 인용된 특허 (8)
Little Wendell L. (Carrollton TX), Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode.
Brabenac, Charles L., Watchdog timer that is disabled upon receiving sleep status signal from monitored device wherein monitored device is not responsive to time-out of watchdog timer.
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