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Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain o

Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.

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1. A memory system, comprising: a plurality of memory devices in a serial chain each memory device in the number of memory devices including: a request input path configured for serial communication through the memory device;a response output path configured for serial communication through the memo

1. A memory system, comprising: a plurality of memory devices in a serial chain each memory device in the number of memory devices including: a request input path configured for serial communication through the memory device;a response output path configured for serial communication through the memory device;a first logic block coupled to the input path to form error recovery data;a second logic block coupled to the output path to recover data using the error recovery data; and a selectable mode to assign any chosen memory device in the plurality of memory devices as an error recovery device. 2. The memory system of claim 1, wherein the selectable mode is only enabled in the last memory device in the chain. 3. The memory system of claim 1, wherein the plurality of memory devices include a plurality of solid state memory devices. 4. The memory system of claim 1, wherein the plurality of memory devices includes a plurality of flash memory devices. 5. The memory system of claim 4, wherein the plurality of flash memory devices includes a number of NAND memory devices. 6. The memory system of claim 1, wherein at least one memory device in the plurality of memory devices includes a stacked die memory device. 7. The memory system of claim 1, wherein at least one memory device in the plurality of memory devices includes a memory sub-chain. 8. The memory system of claim 7, wherein a last memory sub-chain in the plurality of memory devices is enabled as an error recovery device. 9. A memory system, comprising: a plurality of memory devices in a serial chain each memory device in the number of memory devices including: a memory request input;a memory request output configured to pass on memory requests to a downstream memory device;at least one ECC logic block; anda selectable mode to assign any chosen memory device in the plurality of memory devices as an error recovery device. 10. The memory system of claim 9, wherein the selectable mode is only enabled in the last memory device in the chain. 11. The memory system of claim 9, wherein the plurality of memory devices include a plurality of solid state memory devices. 12. The memory system of claim 9, wherein the at least one ECC logic block is configured to form error recovery data by an XOR operation. 13. The memory system of claim 9, wherein the at least one ECC logic block is a single logic block configured to for error recovery data, and to recover data. 14. The solid state memory device of claim 9, wherein the at least one ECC logic block includes a first logic block to form error recovery data and a second logic block to recover data. 15. A solid state memory device, comprising: a memory request input;a memory request output configured to pass on memory requests to a downstream memory device; andat least one ECC logic block, the solid state memory device having a selectable mode to assign the solid state memory device as an error recovery device. 16. The solid state memory device of claim 15, wherein the at least one ECC logic block includes a first logic block to form error recovery data and a second logic block to recover data. 17. The solid state memory device of claim 15, wherein the solid state memory device is a DRAM memory device. 18. The solid state memory device of claim 15, wherein the solid state memory device is a flash memory device. 19. The solid state memory device of claim 15, wherein the flash memory device is a NAND memory device.