[특허]Electrochemical fabrication process for forming multilayer multimaterial microprobe structures

[미국특허] Electrochemical fabrication process for forming multilayer multimaterial microprobe structures 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	C25D-005/02 C25D-005/48 C23C-028/02 G01R-003/00 G01R-001/067 H01L-021/48 C25D-001/00 C23C-018/16
출원번호	US-0431680 (2009-04-28)
등록번호	US-9244101 (2016-01-26)
발명자 / 주소	Cohen, Adam L. Kumar, Ananda H. Lockard, Michael S. Smalley, Dennis R.
출원인 / 주소	University of Southern California
대리인 / 주소	Smalley, Dennis R.
인용정보	피인용 횟수 : 0 인용 특허 : 44

초록 ▼

Some embodiments of the invention are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that partially coats the surface of the probe. Other embodiments are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that completely coats the surface of each layer from which the probe is formed including interlayer regions. These first two groups of embodiments incorporate both the core material and the coating material during the formation of each layer. Still other embodiments are directed to the electrochemical fabrication of microprobe arrays that are partially encapsulated by a dielectric material during a post layer formation coating process. In even further embodiments, the electrochemical fabrication of microprobes from two or more materials may occur by incorporating a coating material around each layer of the structure without locating the coating material in inter-layer regions.

대표청구항 ▼

1. A fabrication process for forming a multi-material, multi-layer three-dimensional structure, comprising: (a) providing an initial multi-material layer on a sacrificial material on a substrate;(b) forming and adhering a first successive multi-material layer to the initial multi-material layer and forming any additional successive multi-material layer or layers on and adhered to the first successive multi-material layer or to a subsequently formed successive multi-material layer to build up a three-dimensional structure from a plurality of adhered multi-material layers,wherein each multi-material layer comprises a first structural material and a sacrificial material,wherein at least one of the adhered multi-material layers further comprises a second structural material, and wherein the three-dimensional structure is formed from the first structural material and the second structural material;(c) after formation of the plurality of adhered multi-material layers, separating the sacrificial material forming part of each of the plurality of adhered multi-material layers to reveal the three-dimensional structure comprising the first structural material and the second structural material;wherein formation of the at least one multi-material layer of the plurality of adhered multi-material layers comprises formation of a first of at least two consecutive multi-material layers and comprises: 1) selectively depositing the sacrificial material into a pattern of photoresist;2) removing the photoresist to yield at least one void that is surrounded on the side by the deposited sacrifical material;3) depositing the first structural material into the void to a thickness less than the thickness of the first of the at least two consecutive layers such that a portion of the at least one void remains that is surround on the bottom and sides by the deposited first structural material;4) depositing the second structural material to occupy the portion of the at least one void that remains after depositing the first structural material;5) planarizing the first structural material, the second structural material, and the sacrificial material to set a boundary level for the first of the at least two consecutive layers;wherein the second structural material is different from the first structural material; andwherein the formation of an additional multi-material layer of the at least two consecutive multi-material layers, which is different from the first of the at least two consecutive multi-material layers, comprises: 1) depositing the sacrificial material and the first structural material for the additional multi-material layer onto a previously formed multi-material layer of the at least two consecutive multi-material layers and then planarizing the sacrificial material and the first structural material to set a boundary level for the additional multi-material layer of the at least two consecutive multi-material layers such that the second structural material deposited to occupy the portion of the at least one void is completely isolated from sacrificial material that is separated in step (c), andwherein the sacrificial material and first and second structural materials are metals and at least one of the depositing steps comprises an electrochemical deposition step. 2. The process of claim 1 wherein the second structural material is the same material as the sacrificial material. 3. The process of claim 1 wherein the first structural material, the second structural material, and the sacrificial material on the first of the at least two consecutive multi-material layers are all different materials. 4. The process of claim 1 wherein the first structural material forming part of at least two of the plurality of multi-materials layers are different materials. 5. The process of claim 1 wherein the depositing of each of the first and second structural materials forming the plurality of multi-material layers occurs by electroplating.

이 특허에 인용된 특허 (44) 인용/피인용 타임라인 분석

Grube, Gary W., Apparatuses and methods for cleaning test probes.
상세보기
Chang Sung Chul ; Khandros Igor Y. ; Smith William D., Chip-scale carrier for semiconductor devices including mounted spring contacts.
상세보기
Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L. ; Dozier Thomas H. ; Smith William D., Contact carriers (tiles) for populating larger substrates with spring contacts.
상세보기
Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Alec Madsen ; Gaetan L. Mathieu, Contact structures with blades having a wiping motion.
상세보기
Eldridge, Benjamin N., Electrical interconnect assemblies and methods.
상세보기
Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Electrochemical fabrication process for forming multilayer multimaterial microprobe structures.
상세보기
Eldridge Benjamin N. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V., Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals.
상세보기
Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
상세보기
Miller Charles A., Filter structures for integrated circuit interfaces.
상세보기
Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.
상세보기
Guckel Henry (Madison WI), Formation of microstructures by multiple level deep X-ray lithography with sacrificial metal layers.
상세보기
Kwon Oh-Kyong (Plano TX) Hashimoto Masashi (Garland TX) Malhi Satwinder (Garland TX) Born Eng C. (Richardson TX), Full wafer integrated circuit testing device.
상세보기
Miller Charles A., High bandwidth passive integrated circuit tester probe card assembly.
상세보기
Eldridge, Benjamin N.; Mathieu, Gaetan, Interconnect assemblies and methods.
상세보기
Khandros, Igor Y; Pedersen, David V.; Whitten, Ralph G., Large contactor with multiple, aligned contactor units.
상세보기
Littlebury Hugh W. (Chandler AZ) Simmons Marion I. (Tempe AZ), Low resistance probe for semiconductor.
상세보기
Bornand Etienne (Boudry CHX), Magnetic microcontactor and manufacturing method thereof.
상세보기
Cohen Adam L., Method for electrochemical fabrication.
상세보기
Yanof Arnold W. (Tempe AZ) Dauksher William (Mesa AZ), Method for manufacturing a probe.
상세보기
Ondricek, Douglas S.; Pedersen, David V., Method for mounting an electronic component.
상세보기
Miller, Charles A.; Long, John M., Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes.
상세보기
Leedy Glenn J. (1061 E. Mountain Dr. Santa Barbara CA 93108), Method of making a flexible tester surface for testing integrated circuits.
상세보기
Grube, Gary W.; Khandros, Igor Y.; Eldridge, Benjamin N.; Mathieu, Gaetan L., Method of manufacturing a probe card.
상세보기
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of mounting resilient contact structures to semiconductor devices.
상세보기
Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of planarizing tips of probe elements of a probe card assembly.
상세보기
Fjelstad, Joseph, Methods and structures for electronic probing arrays.
상세보기
Joseph Fjelstad, Methods and structures for electronic probing arrays.
상세보기
Distefano Thomas H. ; Smith ; Jr. John W., Methods of making connections to a microelectronic unit.
상세보기
Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Methods of removably mounting electronic components to a circuit board, and sockets formed by the methods.
상세보기
Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structures, and methods of making same.
상세보기
Benjamin N. Eldridge ; Gary W. Grube ; Igor Y. Khandros ; Gaetan L. Mathieu, Microelectronic spring contact element and electronic component having a plurality of spring contact elements.
상세보기
Petrarca Kevin S. ; Mih Rebecca D., Microprocessor having air as a dielectric and encapsulated lines and process for manufacture.
상세보기
Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L., Mounting spring elements on semiconductor devices, and wafer-level testing methodology.
상세보기
Mathieu, Gaetan L.; Eldridge, Benjamin N.; Grube, Gary W., Planarizer for a semiconductor contactor.
상세보기
Khandros, Jr., Igor Y.; Sporck, Jr., A. Nicholas; Eldridge, Jr., Benjamin N., Probe card assembly.
상세보기
Benjamin N. Eldridge ; Gary W. Grube ; Gaetan L. Mathieu, Probe card for probing wafers with raised contact elements.
상세보기
Tada Tetsuo (Hyogo JPX) Takagi Ryoichi (Hyogo JPX) Kohara Masanobu (Hyogo JPX), Probing plate for wafer testing.
상세보기
Eslamy, Mohammad; Pedersen, David V; Cobb, Harry D., Segmented contactor.
상세보기
Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
상세보기
Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
상세보기
Benjamin N. Eldridge ; Igor Y. Khandros ; David V. Pedersen ; Ralph G. Whitten, Special contact points for accessing internal circuitry of an integrated circuit.
상세보기
Mathieu, Gaetan L.; Eldridge, Benjamin N.; Grube, Gary W.; Larder, Richard A., Spring interconnect structures.
상세보기
MacIntyre, Donald M., Stress relieved contact array.
상세보기
Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.
상세보기

활용도 분석정보

상세보기

다운로드

내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

내보내기 메뉴

내보내기 구분

파일저장
인쇄
메일전송

구성항목

기본정보
상세정보

관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC

저장형식

Text(ASCII format)
Excel format
PIAS분석(.xls)

메일정보

받는사람 (필수): @
보내는사람 (선택): @
제목
내용: KISTI 검색결과 이메일 서비스

안내

총 건의 자료가 검색되었습니다.

다운받으실 자료의 인덱스를 입력하세요. (1-10,000)

검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다.

데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요)

다운로드 파일은 UTF-8 형태로 저장됩니다.
파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오.

Text(ASCII format)
Excel format

AI-Helper ※ AI-Helper는 을 사용합니다.

AI-Helper

안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

연합인증

[미국특허] Electrochemical fabrication process for forming multilayer multimaterial microprobe structures 원문보기