Method and system for artificially and dynamically limiting the framerate of a graphics processing unit
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/038
G09G-005/00
G06F-015/16
G06F-013/372
G09G-003/36
G09G-005/36
G09G-005/393
G06F-003/14
G06T-001/20
G06T-015/00
G06F-001/32
출원번호
US-0650207
(2009-12-30)
등록번호
US-9256265
(2016-02-09)
발명자
/ 주소
Huang, Jensen
Diard, Franck
Saulters, Scott
출원인 / 주소
NVIDIA CORPORATION
인용정보
피인용 횟수 :
2인용 특허 :
232
초록▼
Embodiments of the present invention are directed to provide a method and system for applying automatic power conservation techniques in a computing system. Embodiments are described herein that automatically limits the frame rate of an application executing in a discrete graphics processing unit op
Embodiments of the present invention are directed to provide a method and system for applying automatic power conservation techniques in a computing system. Embodiments are described herein that automatically limits the frame rate of an application executing in a discrete graphics processing unit operating off battery or other such exhaustible power source. By automatically limiting the frame rate in certain detected circumstances, the rate of power consumption, and thus, the life of the current charge stored in a battery may be dramatically extended. Another embodiment is also provided which allows for the more effective application of automatic power conservation techniques during detected periods of inactivity by applying a low power state immediately after a last packet of a frame is rendered and displayed.
대표청구항▼
1. A method for limiting the frame rate of a graphics processing unit, the method comprising: in a computer system comprising an integrated graphics processing unit (GPU) and a discrete GPU,generating a timestamp in response to a rendering being completed for a current frame of a plurality of frames
1. A method for limiting the frame rate of a graphics processing unit, the method comprising: in a computer system comprising an integrated graphics processing unit (GPU) and a discrete GPU,generating a timestamp in response to a rendering being completed for a current frame of a plurality of frames;comparing the timestamp for the current rendered frame to a timestamp of a previous frame in the plurality of frames corresponding to a most recent power source query to determine if a duration of elapsed time between the respective timestamps exceeds a timing threshold value;querying a current power source of the computer system to determine if the current power source has changed since the most recent power source query when the timestamp of the previous frame exceeds the timing threshold value;in the event the current power source has changed since the most recent power source query, determining if the computer system is being powered by a first power source of a plurality of power sources;in the event the power source comprises the first power source of the plurality of power sources, determining if the discrete GPU is currently in operation; andautomatically limiting a frame rate of the discrete GPU if the frame rate is above a frame rate threshold value in response to a determination that the discrete GPU is currently in operation. 2. The method of claim 1, wherein the frame rate threshold value is user programmable. 3. The method of claim 1, wherein the limiting the frame rate comprises: determining a current frame rate; andstalling a command thread of the GPU if the current frame rate is greater than the frame rate threshold. 4. The method of claim 3, wherein the determining a current frame rate comprises calculating the current frame rate from a plurality of collected timestamps corresponding to recent frames of the application. 5. The method of claim 3 wherein the stalling the command thread of the GPU comprises: inhibiting the transfer of byte code comprising the plurality of commands in a command buffer to the GPU to a frequency that results to a frame rate below the second threshold. 6. The method of claim 3 further comprising putting a graphics rendering process supplying data to be rendered by the integrated GPU or the discrete GPU into a sleep state. 7. The method of claim 1, wherein the first power source comprises a direct current (DC) power source. 8. The method of claim 1, wherein the first power source does not comprise an alternating current (AC) power source. 9. The method of claim 1, wherein a vertical synchronization feature is not in operation for the computer system. 10. The method of claim 1, wherein the determining if the discrete GPU is currently in operation comprises maintaining a framerate in the integrated GPU if the discrete GPU is determined not to be currently in operation. 11. The method of claim 1, wherein the querying a current power source of the computer system to determine if the current power source has changed since a most recent power source query comprises polling the current power source at regular intervals. 12. A system for limiting the frame rate of a graphics processing unit to reduce power consumption comprising: a plurality of graphics processing units comprising a first graphics processing unit and a second graphics processing unit, for rendering graphical output comprising a plurality of frames and a timestamp generated for each of the plurality of frames;a display device for displaying graphical output received from a currently operating graphics processing unit of the plurality of graphics processing units;a central processing unit for distributing a plurality of packets comprising a plurality of rendering instructions to the currently operating graphics processing unit;a plurality of frame buffers respectively comprised in, and corresponding to, the plurality of graphics processing units for storing a plurality of graphics rendering instructions; anda plurality of power sources for providing an operating power source to the system, the plurality of power sources comprising a first power source and a second power source;wherein the plurality of power sources is queried to determine the operating power source when a timestamp between successive frames of the plurality of frames is greater than a timing threshold by comparing the timestamp of a current frame of the plurality of frames to a timestamp of a previous frame of the plurality of frames corresponding to a most recent power source query to determine if a duration of elapsed time between the respective timestamps exceeds a timing threshold value,further wherein, in response to detecting a change in the operating power source from the first power source to the second power source, the currently operating graphics processing unit is determined, and a frame rate of the second graphics processing unit is artificially limited to a threshold value if the second graphics processing unit is determined to be the currently operating graphics processing unit. 13. The system of claim 12, wherein the first graphics processing unit is an integrated graphics processing unit. 14. The system of claim 12, wherein the second graphics processing unit is a discrete graphics processing unit. 15. The system of claim 12, wherein the first power source comprises a direct current power source. 16. The system of claim 12, wherein the second power source comprises an alternating current power source. 17. The system of claim 12, wherein the frame rate of the seconds graphics processing unit is limited by delaying a distribution of the plurality of graphics rendering packets from the central processing unit to the second graphics processing unit to achieve a frame rate produced by the second graphics processing unit below the threshold value. 18. A method for reducing the rate of power consumption of a graphics processing unit, the method comprising: in a computer system comprising an integrated graphics processing unit (GPU) and a discrete GPU, determining which of the integrated GPU and the discrete GPU is currently in operation,in the event a discrete GPU is determined to be currently in operation: receiving a packet of a plurality of packets corresponding to a first frame of a second plurality of frames in a discrete GPU, the packet comprising a plurality of rendering instructions;determining if the packet is a flagged packet;in the event the packet is the flagged packet, determining a type of power source currently supplying power to the computer system; andin response to determining the type of power source currently supplying power to the computer system comprises a battery-operated power source, immediately achieving a low power state in the discrete GPU upon the GPU completes rendering data contained in the flagged packet,wherein the flagged packet comprises a packet flagged as a last packet in a plurality of packets corresponding to a frame of graphical output,further wherein, the determining which of the integrated GPU and the discrete GPU is currently in operation comprises generating a timestamp in response to a rendering being completed for a current frame of a first plurality of frames and comparing the timestamp of the current frame to a timestamp of a previous frame corresponding to a most recent power source query to determine if a duration of elapsed time between the respective timestamps exceeds a timing threshold value. 19. The method of claim 18, wherein the determining if the packet is a flagged packet in the plurality of packets comprises detecting a presence of a flagged packet. 20. The method of claim 18, wherein the immediately achieving a low power state comprises: determining an expected duration of time until a packet of the plurality of packets corresponding to a second frame is received according to a schedule;operating the discrete GPU in the low power state for the expected duration of time. 21. The method of claim 18, wherein a packet of the plurality of packets is received in a frame buffer of the discrete GPU. 22. The method of claim 21, wherein the first frame comprises graphical output for an application executing on the computer system in full-screen display mode.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (232)
Gebara Ghassan R. ; Jansen Kenneth A., Accomodating components.
Huard, Douglas Robert; Burton, Edward Allyn; Wong, Keng L., Altering operating frequency and voltage set point of a circuit in response to the operating temperature and instantaneous operating voltage of the circuit.
Reinhardt Dennis ; Bhat Ketan ; Jackson Robert T. ; Senyk Borys ; Matter Eugene P. ; Gunther Stephen H., Apparatus and method for controlling power usage.
Goodnow Kenneth J. ; Michail Michel S. ; Patel Janak G. ; Pricer Wilbur D. ; Ventrone Sebastian T., Apparatus and method for efficient battery utilization in portable personal computers.
Franke, Jeffery Michael; Johnson, Donald Eugene; Rollins, Michael Scott; Woodham, David Robert, Apparatus, method and program product for automatically distributing power to modules inserted in live chassis.
Seibert Mark H. (Cupertino CA) Wallgren Markus C. (Palo Alto CA), Arrangement for reducing computer power consumption by turning off the microprocessor when inactive.
Katz Neil A. (Parkland FL) Pollitt Richard F. (Highland Beach FL) Suarez Leopoldo L. (Boca Raton FL) Frank C. William (Irvine CA), Battery operated computer operation suspension in response to environmental sensor inputs.
Nakanishi,Tetsuya; Yoshida,Katsuhisa; Ikeda,Masahiro, Charged-particle beam accelerator, particle beam radiation therapy system using the charged-particle beam accelerator, and method of operating the particle beam radiation therapy system.
Hawkins Keith G. (Dripping Springs TX) Wakeland Carl K. (Austin TX), Clock control unit responsive to a power management state for clocking multiple clocked circuits connected thereto.
Marrington S. Paul (P.O. Box 34 Fyshwick CA AUX 2609) Kiankhooy-Fard Paul (1165 Archer St. San Diego CA 92109) Zecos Paul (13367 Caminito Mar Villa Del Mar CA) Rudaw Geoffrey (43 Argow Pl. Nanuet NY , Computer power system.
Ranganathan Ravi (Cupertino CA) Puar Deepraj S. (Sunnyvale CA), Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller.
Kim,Jason Seung Min, Dynamic power management of devices in computer system by selecting clock generator output based on a current state and programmable policies.
Lau Chung Y. (Sunnyvale CA) Farmer Dominic G. (Milpitas CA) Martin Kreg A. (Cupertino CA) Rodal Eric B. (Cupertino CA), GPS receiver having a low power standby mode.
Streitenberger, Robert; Kawai, Hiroyuki; Kobara, Junko; Inoue, Yoshitsugu; Yoshimatsu, Keijiro, Graphic processor having multiple geometric operation units and method of processing data thereby.
Mese Michihiro (Chigasaki JPX) Kamimura Toshio (Fujisawa JPX) Oeda Shigeto (Kamakura JPX) Yonenaga Hitoshi (Hitachi JPX), Information processing apparatus including arrangements for activation to and deactivation from a power-saving state.
Schutz Joseph D. (Portland OR) Rash Bill C. (Saratoga CA), Integrated circuit device that selects its own supply voltage by controlling a power supply.
MacDonald James R ; Gephardt Douglas D. ; Mudgett Dan S., Interrupt controller with external in-service indication for power management within a computer system.
Pham Dac C. (9815 Copper Creek Dr. ; #922 Austin TX 78729) Ventrone Sebastian T. (1 Appletree La. Jericho VT 05465) Raymond Jonathan H. (R.R. #2 ; Box 623 Underhill VT 05489), Logic macro and protocol for reduced power consumption during idle state.
Brock, Bishop Chapman; Hofstee, Harm Peter; Johnson, Mark A.; Keller, Jr., Thomas Walter; Nowka, Kevin John, Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements.
Tran Thang Minh ; Mahalingaiah Rupaka, Method and apparatus for executing plurality of operations per clock cycle in a single processing unit with a self-timed and self-enabled distributed clock.
Holzhammer Gerald S. ; Hernandez Thomas J. ; Mangold Richard P. ; Cadambi Sudarshan Bala, Method and apparatus for managing power consumption of the CPU and on-board system devices of personal computers.
Alben, Jonah; Ma, Dennis Kd; Kelleher, Brian, Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle.
Chris S. Browning ; Shekhar Y. Borkar ; Gregory E. Dermer, Method and apparatus for power throttling in a microprocessor using a closed loop feedback system.
Wang, Chien-Jung; Wang, Shih-Liang; Cheng, Chao-Hao, Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source.
Horden A. Ira ; Gorman Steven D. ; Smith Lionel S., Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control pow.
Nguyen Au H. (Santa Clara CA), Method for reducing power consumption includes comparing variance in number of time microprocessor tried to react input.
Ouelid Abdesselem FR; Dejan Mijuskovic, Methods and circuits for dynamically adjusting a supply voltage and/or a frequency of a clock signal in a digital circuit.
Suzuoki,Masakazu, Multiprocessor system for decrypting and resuming execution of an executing program after transferring the program code between two processors via a shared main memory upon occurrence of predetermined condition.
Georgiou Christos John ; Kirkpatrick Edward Scott ; Larsen Thor Arne, Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit.
Georgiou Christos John ; Kirkpatrick Edward Scott ; Larsen Thor Arne, Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit.
Steven C. Lemke ; Scott R. Johnson ; Eric M. Lunsford ; Nicholas Twyman ; Ronald Marianetti, II ; Neal A. Osborn, Portable computer with differentiated time-out feature.
Smith R. Steven (Saratoga CA) Hanlon Mike S. (San Jose CA) Bailey Robert L. (San Jose CA), Power management for a laptop computer with slow and sleep modes.
Ries Paul S. ; Kinsel John R. ; Riordan Thomas J. ; Thaik Albert M., Processor chip for using an external clock to generate an internal clock and for using data transmit patterns in combina.
Gluseppe La Rosa ; Fernando Guarin ; Kevin Kolvenbach ; Stewart Rauch, III, Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring.
Kurosawa,Minoru; Kawauchi,Kunihiro; Kokami,Yasuhiko, Rotation drive control circuit of multiphases direct current motor and the start-up method thereof.
Ishidera, Nobutaka, Software processing apparatus with a switching processing unit for displaying animation images in an environment operating base on type of power supply.
Atkinson, Lee, System for altering operation of a graphics subsystem during run-time to conserve power upon detecting a low power condition or lower battery charge exists.
Maiocchi Giuseppe,ITX ; Galbiati Ezio,ITX, System for increasing the definition in converting a digital datum in a PWM signal for driving a full-bridge output stage.
Louis B. Hobson, System with control registers for managing computer legacy peripheral devices using an advanced configuration power interface software power management system.
Le, Binh Q.; Yano, Masaru; Yachareni, Santosh K., Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.