Semiconductor integrated circuit and method for operating the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02M-003/158
H03K-017/12
H03K-017/16
H02M-001/00
출원번호
US-0064522
(2013-10-28)
등록번호
US-9257907
(2016-02-09)
우선권정보
JP-2012-282341 (2012-12-26)
발명자
/ 주소
Nomiyama, Takahiro
Tateno, Koji
Kondo, Daisuke
출원인 / 주소
Renesas Electronics Corporation
대리인 / 주소
Mattingly & Malur, PC
인용정보
피인용 횟수 :
2인용 특허 :
6
초록▼
A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one
A switching loss is reduced by reducing a deviation from the operational principle of zero-volt switching (ZVS). A semiconductor integrated circuit includes high-side switch elements Q11 and Q12, a low-side switch element Q2, and a controller CNT. A decoupling capacitance Cin is coupled between one end of a high-side element and an earth potential, and the high-side element includes the first and second transistors Q11 and Q12 coupled in parallel. In changing the high-side elements from an on-state to an off-state, CNT controls Q12 from an on-state to an off-state by delaying Q12 relative to Q11. Q11 and Q12 are divided into a plurality of parts inside a semiconductor chip Chip 1, a plurality of partial first transistors formed by dividing Q11 and a plurality of partial second transistors formed by dividing Q12 are alternately arranged in an arrangement direction of Q11 and Q12, inside the semiconductor chip Chip 1.
대표청구항▼
1. A semiconductor integrated circuit comprising a high-side switch element, a low-side switch element, and a controller, wherein an input voltage can be supplied to one end of the high-side switch element via a decoupling inductor, other end of the high-side switch element and one end of the low-si
1. A semiconductor integrated circuit comprising a high-side switch element, a low-side switch element, and a controller, wherein an input voltage can be supplied to one end of the high-side switch element via a decoupling inductor, other end of the high-side switch element and one end of the low-side switch element are coupled to a switching node, and other end of the low-side switch element can be coupled to an earth potential,wherein the controller can drive the high-side switch element in an on-state and an off-state,wherein the switching node can be coupled to a low pass filter including a smoothing inductor and a smoothing capacitor,wherein a decoupling capacitor can be coupled between the one end of the high-side switch element and the earth potential,wherein the high-side switch element includes a first transistor and a second transistor whose current paths are coupled in parallel between the one end of the high-side switch element and the other end of the high-side switch element,wherein in changing a state between the one end of the high-side switch element and the other end of the high-side switch element from an on-state to an off-state, the controller controls the second transistor from the on-state to the off-state by delaying the second transistor relative to the first transistor,wherein each transistor of the first transistor and the second transistor is formed to be divided into a plurality of parts, inside a semiconductor chip, andwherein a plurality of partial first transistors formed by dividing the first transistor and a plurality of partial second transistors formed by dividing the second transistor are alternately arranged in an arrangement direction of the first transistor and the second transistor, inside the semiconductor chip. 2. The semiconductor integrated circuit according to claim 1, wherein the low-side switch element includes a third transistor whose current path is coupled between the switching node and the earth potential. 3. The semiconductor integrated circuit according to claim 2, wherein the controller generates a first high-side driving signal for driving a control input terminal of the first transistor, a second high-side driving signal for driving a control input terminal of the second transistor, and a low-side driving signal for driving a control input terminal of the third transistor, andwherein the first high-side driving signal and the second high-side driving signal are substantially in-phase, whereas the first high-side driving signal as well as the second high-side driving signal, and the low-side driving signal are substantially anti-phase. 4. The semiconductor integrated circuit according to claim 3, wherein an output voltage of a DC-DC converter generated from the low pass filter is set by an on period during which the high-side switch element is in the on-state, an off period during which the high-side switch element is in the off-state, and the input voltage. 5. The semiconductor integrated circuit according to claim 4, wherein the first transistor, the second transistor, and the third transistor are N-channel MOS transistors, respectively. 6. The semiconductor integrated circuit according to claim 5, wherein the first transistor and the second transistor as the high-side switch elements are formed in a first semiconductor chip,wherein the third transistor as the low-side switch element is formed in a second semiconductor chip,wherein the controller is formed in a third semiconductor chip, andwherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are sealed into one package. 7. The semiconductor integrated circuit according to claim 6, wherein the first transistor and the second transistor as the high-side switch elements are formed by a trench-gate-type N-channel vertical MOS transistor structure, andwherein a plurality of trench gates of the first transistor and a plurality of trench gates of the second transistor are alternately arranged in the arrangement direction of the first transistor and the second transistor, inside the first semiconductor chip. 8. The semiconductor integrated circuit according to claim 7, wherein the third transistor as the low-side switch element is formed by the trench-gate-type N-channel vertical MOS transistor structure. 9. The semiconductor integrated circuit according to claim 8, wherein the one package, the decoupling inductor, the decoupling capacitor, the smoothing inductor, and the smoothing capacitor comprise a DC-DC converter of a switching regulator system. 10. The semiconductor integrated circuit according to claim 5, wherein the first transistor and the second transistor as the high-side switch elements, the third transistor as the low-side switch element, and the controller are integrated and formed in a single semiconductor chip, andwherein the single semiconductor chip is sealed into one package. 11. The semiconductor integrated circuit according to claim 10, wherein the first transistor and the second transistor as the high-side switch elements are formed by a planer-type N-channel lateral MOS transistor structure, andwherein a plurality of gates of the first transistor and a plurality of gates of the second transistor are alternately arranged in the arrangement direction of the first transistor and the second transistor, inside the single semiconductor chip. 12. The semiconductor integrated circuit according to claim 11, wherein the third transistor as the low-side switch element is formed by the planer-type N-channel lateral MOS transistor structure inside the single semiconductor chip. 13. The semiconductor integrated circuit according to claim 12, wherein the single semiconductor chip, the decoupling inductor, the decoupling capacitor, the smoothing inductor, and the smoothing capacitor comprise a DC-DC converter of a switching regulator system. 14. A method for operating a semiconductor integrated circuit comprising a high-side switch element, a low-side switch element, and a controller, wherein an input voltage can be supplied to one end of the high-side switch element via a decoupling inductor, other end of the high-side switch element and one end of the low-side switch element are coupled to a switching node, and other end of the low-side switch element can be coupled to an earth potential,wherein the controller can drive the high-side switch element in an on-state and an off-state,wherein the switching node can be coupled to a low pass filter including a smoothing inductor and a smoothing capacitor,wherein a decoupling capacitor can be coupled between the one end of the high-side switch element and the earth potential,wherein the high-side switch element includes a first transistor and a second transistor whose current paths are coupled in parallel between the one end of the high-side switch element and the other end of the high-side switch element,wherein in changing the state between the one end of the high-side switch element and the other end of the high-side switch element from an on-state to an off-state, the controller controls the second transistor from the on-state to the off-state by delaying the second transistor relative to the first transistor,wherein each transistor of the first transistor and the second transistor is formed to be divided into a plurality of parts, inside a semiconductor chip, andwherein a plurality of partial first transistors formed by dividing the first transistor and a plurality of partial second transistors formed by dividing the second transistor are alternately arranged in an arrangement direction of the first transistor and the second transistor, inside the semiconductor chip. 15. The method according to claim 14, wherein the low-side switch element includes a third transistor whose current path is coupled between the switching node and the earth potential. 16. The method according to claim 15, wherein the controller generates a first high-side driving signal for driving a control input terminal of the first transistor, a second high-side driving signal for driving a control input terminal of the second transistor, and a low-side driving signal for driving a control input terminal of the third transistor, andwherein the first high-side driving signal and the second high-side driving signal are substantially in-phase, whereas the first high-side driving signal as well as the second high-side driving signal and the low-side driving signal are substantially anti-phase. 17. The method according to claim 16, wherein an output voltage of a DC-DC converter generated from the low pass filter is set by an on period during which the high-side switch element is in the on-state, an off period during which the high-side switch element is in the off-state, and the input voltage. 18. The method according to claim 17, wherein the first transistor, the second transistor, and the third transistor are N-channel MOS transistors, respectively. 19. The method according to claim 15, wherein the first transistor and the second transistor as the high-side switch elements are formed in a first semiconductor chip,wherein the third transistor as the low-side switch element is formed in a second semiconductor chip, whereinthe controller is formed in a third semiconductor chip, andwherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are sealed into one package. 20. The method according to claim 19, wherein the first transistor and the second transistor as the high-side switch elements are formed by a trench-gate-type N-channel vertical MOS transistor structure, andwherein a plurality of trench gates of the first transistor and a plurality of trench gates of the second transistor are alternately arranged in the arrangement direction of the first transistor and the second transistor, inside the first semiconductor chip.
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