Energy lockout in response to a planar catastrophic fault
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02H-011/00
H02H-007/20
H02H-003/08
G06F-001/26
출원번호
US-0278520
(2014-05-15)
등록번호
US-9367110
(2016-06-14)
발명자
/ 주소
Barnette, Jamaica L.
Clemo, Raymond M.
Evans, Douglas I.
Totten, Brian C.
출원인 / 주소
Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
대리인 / 주소
Brown, Katherine S.
인용정보
피인용 횟수 :
0인용 특허 :
6
초록▼
A computer planar includes an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high. During normal operation, an auxiliary power source maintains an active high enable signal on the en
A computer planar includes an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high. During normal operation, an auxiliary power source maintains an active high enable signal on the enable signal line, which includes a fuse. However, a fault protection circuit coupled to the enable signal line can pull down the enable signal line in response to a fault, such that the fuse is permanently opened. Once the fuse is open, the external power supply cannot be enabled and further damage to the computer planar is prevented.
대표청구항▼
1. A computer planar, comprising: an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high;an auxiliary power source for maintaining an active high enable signal on the enable signal l
1. A computer planar, comprising: an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high;an auxiliary power source for maintaining an active high enable signal on the enable signal line;a fuse coupled between the auxiliary power source and the enable signal line; andone or more fault protection circuits coupled to the enable signal line, wherein each fault protection circuit can pull down the enable signal line and open the fuse in response to a fault. 2. The computer planar of claim 1, further comprising: a hot swap controller for selectively coupling to a hot swap device that distributes power, wherein the hot swap controller has an enable input coupled to the enable signal line, and wherein the hot swap controller will not enable the hot swap device unless the enable signal is active high. 3. The computer planar of claim 1, wherein the one or more fault protection circuits includes a sensing or reporting device. 4. The computer planar of claim 1, wherein the fuse is a pull-up fuse. 5. The computer planar of claim 1, wherein each fault protection circuit can pull down the enable signal line with an open drain. 6. The computer planar of claim 1, further comprising: a pair of junctions in the enable signal line on either side of the fuse, wherein the pair of junctions are configured for receiving a jumper around the fuse, wherein manual installation of the jumper serves to override the fuse after it has been opened. 7. The computer planar of claim 1, further comprising: a second enable signal line for providing a second enable signal to a second external power supply or second hot swap controller, wherein the second external power supply or second hot swap controller will not turn on unless the enable signal is active high;a second auxiliary power source for maintaining an active high enable signal on the second enable signal line;a second fuse coupled between the second auxiliary power source and the second enable signal line; andone or more second fault protection circuits coupled to the second enable signal line, wherein each second fault protection circuit can pull down the second enable signal line and open the second fuse in response to a fault, wherein opening the second fuse prevents the second enable signal line from being active high but does not prevent the first enable signal line from being active high. 8. The computer planar of claim 7, wherein the first auxiliary power source and second auxiliary power source are the same power source. 9. A method comprising: providing an active high enable signal on an enable signal line to an external power supply during normal operation of a computer planar, wherein the enable signal line includes a fuse coupling the enable signal line to an auxiliary power source;pulling down the enable signal line in response to detecting a fault, wherein pulling down the enable signal line causes the fuse to open, and wherein opening the fuse prevents enabling of the external power supply. 10. The method of claim 9, wherein the enable signal line is pulled down by one or more fault protection circuits coupled to the enable signal line in response to the one or more fault protection circuits detecting the fault. 11. The method of claim 10, wherein the one or more fault protection circuits includes a sensing or reporting device. 12. The method of claim 10, wherein the one or more fault protection circuits can pull down the enable signal line with an open drain. 13. The method of claim 9, further comprising: providing the active high enable signal to a hot swap controller coupled to a hot swap device that distributes power, wherein opening the fuse prevents the hot swap controller from enabling the hot swap device. 14. The method of claim 9, wherein the fuse is a pull-up fuse.
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이 특허에 인용된 특허 (6)
Bowden, Scott J.; Douglas, Jonathan P., Failsafe mechanism for preventing an integrated circuit from overheating.
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