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A method for operating a computing system with a trusted processor include generating a secret cryptographic key based on a physically unclonable function in at least one hardware component in the trusted processor, generating a first public key and first private key using first secret cryptographic

A method for operating a computing system with a trusted processor include generating a secret cryptographic key based on a physically unclonable function in at least one hardware component in the trusted processor, generating a first public key and first private key using first secret cryptographic key, and executing instruction code corresponding to a first software program. The method further includes generating output data with the trusted processor during execution of the first software program, generating encrypted data corresponding to the output data using the first public key for at least a portion of the encryption, generating a signature of the encrypted data, and transmitting with an input/output (I/O) interface operatively connected to the trusted processor the encrypted data and the signature for storage in an untrusted memory.

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1. A method for operating a computing system comprising: generating with a trusted processor a first secret cryptographic key based on a physically unclonable function in a volatile cache memory in the trusted processor, the first secret cryptographic key being unavailable to other components in the

1. A method for operating a computing system comprising: generating with a trusted processor a first secret cryptographic key based on a physically unclonable function in a volatile cache memory in the trusted processor, the first secret cryptographic key being unavailable to other components in the computing system;generating with the trusted processor a first asymmetric cryptographic key pair with reference to the first secret cryptographic key and a predetermined asymmetric cryptographic key generation process, the first asymmetric cryptographic key pair including a first public key and a first private key;executing with the trusted processor instruction code stored in the volatile cache memory corresponding to a first software program;receiving with the trusted processor input data for the first software program and first authentication data for the input data from an untrusted memory device through an input output (I/O) interface operatively connected to the trusted processor;executing with the trusted processor the instruction code stored in the volatile cache memory corresponding to the first software program to process the input data and generate output data only in response to verifying with the trusted processor that the input data correspond to the first software program with reference to the first private key and the authentication data;generating with the trusted processor first encrypted data corresponding to the output data;generating with the trusted processor second authentication data for the first encrypted data; andtransmitting with the I/O interface the first encrypted data and the second authentication data for storage in an untrusted memory. 2. The method of claim 1 further comprising: receiving with the I/O interface operatively connected to the trusted processor second encrypted data corresponding to a second secret cryptographic key from a verifier computing device that is external to the trusted processor;decrypting with the trusted processor the second encrypted data corresponding to the second secret cryptographic key with the first private key; andgenerating with the trusted processor second encrypted data corresponding to the output data with the second cryptographic key; andtransmitting with the I/O interface operatively connected to the trusted processor the second encrypted data to the verifier computing device. 3. The method of claim 2 further comprising: generating with the trusted processor a first hash value of input data received by the trusted processor for the first software program;generating with the trusted processor a second hash value for program state data of the first software program; andgenerating with the trusted processor the second encrypted data including encrypted data corresponding to the first hash value and the second hash value using the second secret cryptographic key. 4. The method of claim 1 further comprising: generating with the trusted processor a hash value corresponding to the instruction code of the first software program;generating with the trusted processor the second authentication data for the first encrypted data with the first private key as a signature corresponding to the output data and the hash value corresponding to the instruction code of the first software program. 5. The method of claim 1 further comprising: receiving with the I/O interface operatively connected to the trusted processor the first encrypted data and the second authentication data from the untrusted memory;verifying with the trusted processor the authentication data corresponding to the encrypted data with reference to the first public key; andgenerating with the trusted processor decrypted data corresponding to the output data only in response to successful verification of the authentication data. 6. The method of claim 1 further comprising: generating with the trusted processor a first hash value corresponding to the instruction code of the first software program;generating with the trusted processor a second secret cryptographic key with reference to the first secret cryptographic key and the first hash value, the second secret cryptographic key being unavailable to other components in the computing system; andgenerating with the trusted processor the authentication data as a message authentication code corresponding to the encrypted data with reference to the second secret key. 7. The method of claim 6 further comprising: receiving with the I/O interface operatively connected to the trusted processor the encrypted data and the message authentication code from the untrusted memory;verifying with the trusted processor the message authentication code with reference to the second secret cryptographic key; andgenerating with the trusted processor decrypted output data from the encrypted data for the first software program with reference to the second secret cryptographic key only in response to successful verification of the message authentication code. 8. The method of claim 1, the generation of the first secret cryptographic key further comprising: receiving with the I/O interface operatively connected to the trusted processor seed data that correspond to a user of the computing system; andgenerating the first secret cryptographic key based on the physically unclonable function of the at least one hardware component and the seed data to generate the first secret cryptographic key for the user that is different from another secret cryptographic key generated in response to different seed data corresponding to another user. 9. The method of claim 1 wherein the trusted processor only stores the first secret cryptographic key, the first private key, and the output data of the first software program prior to encryption in the volatile cache memory in the trusted processor. 10. The method of claim 9 further comprising: deleting with the trusted processor contents of the volatile cache memory in the trusted processor including the first secret cryptographic key, the first private key, the instruction code corresponding to the first software program, and the output data of the first software program; andoperating the trusted processor in an untrusted mode after the deletion. 11. A computing system comprising: an untrusted memory configured to store data;an input output (I/O) interface configured to send and receive data from the untrusted memory; anda trusted processor operatively connected to the untrusted memory and the I/O interface, the trusted processor comprising a volatile cache memory and the trusted processor being configured to: generate a first secret cryptographic key based on a physically unclonable function in the volatile cache memory, the first secret cryptographic key being unavailable to other components in the computing system;generate a first asymmetric cryptographic key pair with reference to the first secret cryptographic key and a predetermined asymmetric cryptographic key generation process, the first asymmetric cryptographic key pair including a first public key and a first private key;execute instruction code corresponding to a first software program to generate output data;generate first encrypted data corresponding to the output data;generate authentication data for the first encrypted data; andtransmit with the input/output (I/O) interface the first encrypted data and the authentication data for storage in the untrusted memory. 12. The system of claim 11, the I/O interface being further configured to: receive data from and transmit data to a verifier computing device that is external to the trusted processor; andthe trusted processor being further configured to: receive second encrypted data corresponding to a second secret cryptographic key from the verifier computing device;decrypt the second encrypted data corresponding to the second secret cryptographic key with the first private key;generate second encrypted data corresponding to the output data with the second cryptographic key; andtransmit with the I/O interface the second encrypted data to the verifier computing device. 13. The system of claim 12, the trusted processor being further configured to: generate a first hash value corresponding to input data received by the trusted processor for the first software program;generate a second hash value corresponding to program state data of the first software program; andencrypt the first hash value and the second hash value using the second secret cryptographic key for transmission to the verifier computing device through the I/O interface. 14. The system of claim 11, the trusted processor being further configured to: generate a hash value corresponding to the instruction code of the first software program;generate the second authentication data for the first encrypted data with the first private key as a signature corresponding to the output data and the hash value corresponding to the instruction code of the first software program. 15. The system of claim 11, the trusted processor being further configured to: receive with the I/O interface the first encrypted data and the second authentication data from the untrusted memory;verify the authentication data corresponding to the encrypted data with reference to the first public key; andgenerate with the trusted processor decrypted data corresponding to the output data only in response to successful verification of the authentication data. 16. The system of claim 11, the trusted processor being further configured to: generate a first hash value corresponding to the instruction code of the first software program;generate a second secret cryptographic key with reference to the first secret cryptographic key and the first message hash value, the second secret cryptographic key being unavailable to other components in the computing system; andgenerate with the trusted processor the authentication data as a message authentication code corresponding to the encrypted data with reference to the second secret key. 17. The system of claim 16, the trusted processor being further configured to: receive with the I/O interface operatively connected to the trusted processor the encrypted data and the message authentication code from the untrusted memory;verify with the trusted processor the message authentication code with reference to the second secret cryptographic key; andgenerate with the trusted processor decrypted output data from the encrypted data for the first software program with reference to the second secret cryptographic key only in response to successful verification of the message authentication code. 18. The system of claim 11, the trusted processor being further configured to: receive with the I/O interface seed data that correspond to a user of the computing system; andgenerate the first secret cryptographic key based on the physically unclonable function of the at least one hardware component and the seed data to generate the first secret cryptographic key for the user that is different from another secret cryptographic key generated in response to different seed data corresponding to another user. 19. The system of claim 11, the trusted processor further comprising: a volatile memory; andthe trusted processor being further configured to: only store the first secret cryptographic key, the first private key, and the output data of the first software program prior to encryption in the volatile cache memory. 20. The system of claim 19, the trusted processor being further configured to: delete contents of the volatile cache memory including the first secret cryptographic key, the first private key, the instruction code corresponding to the first software program, and the output data of the first software program; andoperate in an untrusted mode after the deletion.