System and method for distributed voltage regulator-gating
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-001/10
G05F-001/56
출원번호
US-0549120
(2014-11-20)
등록번호
US-9372490
(2016-06-21)
발명자
/ 주소
Kose, Selcuk
Uzun, Orhun Aras
출원인 / 주소
University of South Florida
대리인 / 주소
Sauter, Molly L.
인용정보
피인용 횟수 :
0인용 특허 :
7
초록▼
A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when
A system and method for adaptive activity management of on-chip voltage regulators based upon the workload information is provided to force each on-chip regulator to operate in its most power-efficient load current. In the proposed regulator-gating technique, regulators are adaptively turned ON when the current demand is high and turned OFF when the current demand is low to improve the voltage conversion efficiency. With the proposed regulator-gating system and method, the overall voltage conversion efficiency from the battery or off-chip power supply to the output of the on-chip voltage regulators experiences an approximately 3 times improvement over the prior art techniques.
대표청구항▼
1. A method for adaptive management of an on-chip distributed power network, the on-chip distributed power network comprising a set of on-chip voltage regulators coupled in parallel to one or more load circuits, the method comprising: determining an output current at a selected power-conversion effi
1. A method for adaptive management of an on-chip distributed power network, the on-chip distributed power network comprising a set of on-chip voltage regulators coupled in parallel to one or more load circuits, the method comprising: determining an output current at a selected power-conversion efficiency level for each of the on-chip voltage regulators included in the set of on-chip voltage regulators;determining a current demand of the one or more load circuits coupled to the on-chip voltage regulators;sensing, with a first voltage regulator coupled in parallel with the set of on-chip voltage regulators, an output voltage of the one or more load circuits;providing a current from the first voltage regulator to the on-chip distributed power network in response to a drop in the output voltage of the one or more load circuits; andturning ON a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators of the set of on-chip voltage regulators at the selected power-conversion efficiency level, while the first voltage regulator is providing the current to the on-chip distributed power network. 2. The method of claim 1, wherein the selected power-conversion efficiency level is a highest efficiency level. 3. The method of claim 1, wherein the subset of the set of on-chip voltage regulators is a minimum number of on-chip voltage regulators required to meet the current demand of the one or more load circuits based at least in part on the output current of each of the plurality of on-chip voltage regulators. 4. The method of claim 1, wherein the first voltage regulator is a digital low-dropout voltage regulator and the method, further comprises: wherein sensing, with a first voltage regulator coupled in parallel with the set of on-chip voltage regulators, an output voltage of the one or more load circuits further comprises, sensing, with a voltage sensing circuit of the digital low-dropout voltage regulator, the output voltage of the one or more load circuits;generating, by the voltage sensing circuit of the digital low-dropout voltage regulator, a gate control voltage in response to a drop in the output voltage of the one or more load circuits;controlling a gate voltage of a pass transistor of the digital low-dropout voltage regulator using the gate control voltage generated b the voltage sensing circuit;wherein providing a current from the first voltage regulator to the on-chip distributed power network in response to a drop in the output voltage of the one or more load circuits, further comprises, providing the current from the pass transistor of the digital low-dropout voltage regulator, to the on-chip distributed power network in response to the drop in output voltage of the one or more load circuits; andwherein turning ON a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators of the set of on-chip voltage regulators at the selected power-conversion efficiency level, while the first voltage regulator is providing the current to the on-chip distributed power network further comprises, turning ON the subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators of the set of on-chip voltage regulators at the selected power-conversion efficiency level, while the pass transistors of the digital low-dropout voltage regulator is providing the current to the on-chip distributed power network in response to the drop in output voltage of the one or more load circuits. 5. The method of claim 1, further comprising: determining the available power budget of the on-chip distributed power network;identifying the subset of on-chip voltage regulators that have been turned ON; andturning OFF one or more of the on-chip voltage regulators of the subset of on-chip voltage regulators if the power budget is not satisfied by the subset of on-chip voltage regulators that have been turned ON. 6. The method of claim 1, wherein turning ON a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators of the set of on-chip voltage regulators at the selected power-conversion efficiency level, while the first voltage regulator is providing the current to the on-chip distributed power network, further comprises: sensing, with the first voltage regulator coupled in parallel with the set of on-chip voltage regulators, an output voltage of the on-chip distributed power network;providing a current, from the first voltage regulator, to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network; andturning ON the subset of the on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators of the set of on-chip voltage regulators at the selected power-conversion efficiency level while the first voltage regulator is providing a current to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network. 7. The method of claim 6, further comprising disabling the current from the voltage sensing circuit after the subset of on-chip voltage regulators have been turned ON. 8. The method of claim 6, wherein the first voltage regulator is a digital low-dropout voltage regulator, the method further comprising: sensing the output voltage of the on-chip distributed power network, with a voltage sensing circuit of the digital low-dropout voltage regulator;generating, by the voltage sensing circuit of the digital low-dropout voltage regulator, a gate control voltage in response to the drop in the output voltage of the on-chip distributed power network;controlling a gate voltage of a pass transistor of the digital low-dropout voltage regulator using the gate control voltage generated by the voltage sensing circuit;wherein providing the current, from the digital low-dropout voltage regulator, to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network further comprises, providing the current from the pass transistor of the digital low-dropout voltage regulator, to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network; andwherein turning ON the subset of the on-chip voltage regulators while the digital low drop-out voltage regulator is providing the current to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network further comprises, turning ON the subset of the on-chip voltage regulators while the pass transistor of the digital low drop-out voltage regulator is providing the current to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network. 9. The method of claim 6, further comprising, prior to turning ON a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators of the set of on-chip voltage regulators at the selected power-conversion efficiency level, while the first voltage regulator is providing the current to the on-chip distributed power network, asserting a turn-on signal to the subset of on-chip voltage regulators. 10. The method of claim 1, wherein the set of on-chip voltage regulators are selected from the group consisting of low-dropout voltage regulators, switched capacitor voltage regulators and buck converter voltage regulators. 11. A method for adaptive management of an on-chip distributed power network comprising a set of on-chip voltage regulators coupled in parallel to one or more load circuits, the method comprising: determining an output current at a selected power-conversion efficiency level for each of the on-chip voltage regulators included in the set of on-chip voltage regulators;determining a current demand of the one or more load circuits coupled to the on-chip voltage regulators;sensing, with a voltage sensing circuit of at least one digital low-dropout voltage regulator coupled in parallel with the set of on-chip voltage regulators, an output voltage of the on-chip distributed power network;generating, by the voltage sensing circuit of the at least one digital low-dropout voltage regulator, a gate control voltage in response to a drop in the output voltage of the on-chip distributed power network;controlling a gate voltage of a pass transistor of the digital low-dropout voltage regulator using the gate control voltage generated by the at least one digital low-dropout voltage regulator;providing a current, from the pass transistor of the digital low-dropout voltage regulator, to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network; andactivating a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators at the selected power-conversion efficiency level. 12. The method of claim 11, further comprising disabling the current from the pass transistor after the subset of on-chip voltage regulators have been activated. 13. A system for adaptive management of an on-chip distributed power network, the system comprising: an on-chip distributed power network comprising a set of on-chip voltage regulators coupled in parallel to one or more load circuits, each of the on-chip voltage regulators of the set of on-chip voltage regulators having an output current equal to the output current of the voltage regulator at a selected efficiency level;one or more power sensors configured for determining a current demand of the one or more load circuits coupled to the set of on-chip voltage regulators;a first voltage regulator configured for sensing an output voltage of the on-chip distributed power network and configured for providing a current to the on-chip distributed power network in response to a drop in output voltage of the on-chip distributed power network; anda power controller coupled to the on-chip distributed power network, the power controller configured for turning ON a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current of each of the on-chip voltage regulators at the selected power-conversion efficiency level, while the first voltage regulator is providing a current to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network. 14. The system of claim 13, wherein the selected power-conversion efficiency level is a highest efficiency level. 15. The system of claim 13, wherein the subset of the set of on-chip voltage regulators is a minimum number of on-chip voltage regulators required to meet the current demand of the one or more load circuits based at least in part on the output current of each of the plurality of on-chip voltage regulators. 16. The system of claim 13, wherein the power controller is further configured for determining the available power budget of the on-chip distributed power network determining the available power budget of the on-chip distributed power network, for identifying the on-chip voltage regulators that have been turned ON and for turning OFF one or more of the subset of voltage regulators if the power budget is not satisfied by the on-chip voltage regulators that have been turned ON. 17. The system of claim 13, wherein the first voltage regulator is a digital low-dropout voltage regulator coupled in parallel with the set of on-chip voltage regulators, the digital low-dropout voltage regulator comprising a voltage sensing circuit and a pass transistor coupled to the voltage sensing circuit, the voltage sensing circuit configured for sensing the output voltage of the on-chip distributed power network and configured for generating a gate control voltage in response to the drop in the output voltage of the on-chip distributed power network and the pass transistor configured for providing the current to the on-chip distributed power network in response to the drop in output voltage of the on-chip distributed power network; and the power controller further configured for turning ON the subset of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current at the selected efficiency level of each of the set of on-chip voltage regulators while the digital low-dropout voltage regulator is providing a current to the on-chip distributed power network. 18. The system of claim 17, further comprising disabling the current from the pass transistor after the subset of on-chip voltage regulators have been turned ON. 19. The system of claim 17, wherein the voltage sensing circuit comprises two skewed inverters. 20. The system of claim 17, further comprising, prior to turning ON a subset of the set of on-chip voltage regulators based at least in part on the current demand of the one or more load circuits and the output current at the selected efficiency level of each of the set of on-chip voltage regulators, asserting a turn-on signal to the subset of on-chip voltage regulators. 21. The system of claim 15, wherein the set of on-chip voltage regulators are selected from the group consisting of low-dropout voltage regulators, switched capacitor voltage regulators and bus converter voltage regulators.
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이 특허에 인용된 특허 (7)
Hsu Louis Lu-Chen ; Kirihata Toshiaki ; Ratanaphanyarat Somnuk ; Shin Hyun Jong, High performance on-chip voltage regulator designs.
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