최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0605946 (2015-01-26) |
등록번호 | US-9424387 (2016-08-23) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 549 |
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists betw
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.
1. An integrated circuit, comprising: a first cell configured to provide a logic function, the first cell configured in accordance with a first cell phasing, the first cell phasing defined by a first index value for conductive structure placements in a gate level and a second index value for conduct
1. An integrated circuit, comprising: a first cell configured to provide a logic function, the first cell configured in accordance with a first cell phasing, the first cell phasing defined by a first index value for conductive structure placements in a gate level and a second index value for conductive structure placements in a second interconnect level located two interconnect levels above the gate level, each of the first and second index values corresponding to a respective distance measured from a left boundary of the first cell and in a direction perpendicular to the left boundary of the first cell; anda second cell configured to provide a logic function, the second cell configured in accordance with a second cell phasing, the second cell phasing defined by a third index value for conductive structure placements in the gate level and a fourth index value for conductive structure placements in the second interconnect level, each of the third and fourth index values corresponding to a respective distance measured from a left boundary of the second cell and in a direction perpendicular to the left boundary of the second cell,wherein the second cell is positioned next to the first cell such that the left boundary of the second cell is aligned with a right boundary of the first cell,wherein conductive structures within the gate level of each of the first and second cells are positioned in accordance with a first virtual grate defined by a first series of parallel and equally spaced lines oriented to extend lengthwise in a first direction over an underlying substrate,wherein conductive structures within the second interconnect level of each of the first and second cells are positioned in accordance with a second virtual grate defined by a second series of parallel and equally spaced lines oriented to extend lengthwise in the first direction,wherein the first and second virtual grates are indexed to a common spatial location,wherein the first virtual grate is defined by a first grate pitch as measured in a second direction perpendicular to the first direction between any two adjacently positioned lines of the first virtual grate, and the second virtual grate is defined by a second grate pitch as measured in the second direction perpendicular between any two adjacently positioned lines of the second virtual grate,wherein the second grate pitch is equal to the first grate pitch multiplied by a ratio of integer values. 2. The integrated circuit as recited in claim 1, wherein the logic function of the first cell is the same as the logic function of the second cell. 3. The integrated circuit as recited in claim 1, wherein the logic function of the first cell is different than the logic function of the second cell. 4. The integrated circuit as recited in claim 1, wherein the left and right boundaries of the first cell are oriented in the first direction. 5. The integrated circuit as recited in claim 4, wherein an overall size of the first cell as measured in the second direction is substantially equal to an overall size the second cell as measured in the second direction. 6. The integrated circuit as recited in claim 4, wherein an overall size of the first cell as measured in the second direction is different than an overall size the second cell as measured in the second direction. 7. The integrated circuit as recited in claim 1, wherein the first index value is substantially equal to the third index value. 8. The integrated circuit as recited in claim 7, wherein the third index value is substantially equal to the fourth index value. 9. The integrated circuit as recited in claim 7, wherein the third index value is different than the fourth index value. 10. The integrated circuit as recited in claim 1, wherein the first index value is different than the second index value, and wherein the third index value is different than the fourth index value. 11. A method for defining a layout of an integrated circuit, comprising: defining a layout of a first cell configured to provide a logic function, the first cell layout defined in accordance with a first cell phasing, the first cell phasing defined by a first index value for conductive structure placements in a gate level and a second index value for conductive structure placements in a second interconnect level located two interconnect levels above the gate level, each of the first and second index values corresponding to a respective distance measured from a left boundary of the first cell and in a direction perpendicular to the left boundary of the first cell;defining a layout of a second cell configured to provide a logic function, the second cell layout defined in accordance with a second cell phasing, the second cell phasing defined by a third index value for conductive structure placements in the gate level and a fourth index value for conductive structure placements in the second interconnect level, each of the third and fourth index values corresponding to a respective distance measured from a left boundary of the second cell and in a direction perpendicular to the left boundary of the second cell;positioning the second cell next to the first cell such that the left boundary of the second cell is aligned with a right boundary of the first cell;positioning conductive structures within the gate level of each of the first and second cells in accordance with a first virtual grate defined by a first series of parallel and equally spaced lines oriented to extend lengthwise in a first direction over an underlying substrate; andpositioning conductive structures within the second interconnect level of each of the first and second cells in accordance with a second virtual grate defined by a second series of parallel and equally spaced lines oriented to extend lengthwise in the first direction,wherein the first and second virtual grates are indexed to a common spatial location,wherein the first virtual grate is defined by a first grate pitch as measured in a second direction perpendicular to the first direction between any two adjacently positioned lines of the first virtual grate, and the second virtual grate is defined by a second grate pitch as measured in the second direction perpendicular between any two adjacently positioned lines of the second virtual grate,wherein the second grate pitch is equal to the first grate pitch multiplied by a ratio of integer values. 12. The method as recited in claim 11, wherein the logic function of the first cell is the same as the logic function of the second cell. 13. The method as recited in claim 11, wherein the logic function of the first cell is different than the logic function of the second cell. 14. The method as recited in claim 11, wherein the left and right boundaries of the first cell are oriented in the first direction. 15. The method as recited in claim 14, wherein an overall size of the first cell as measured in the second direction is substantially equal to an overall size the second cell as measured in the second direction. 16. The method as recited in claim 14, wherein an overall size of the first cell as measured in the second direction is different than an overall size the second cell as measured in the second direction. 17. The method as recited in claim 11, wherein the first index value is substantially equal to the third index value. 18. The method as recited in claim 17, wherein the third index value is substantially equal to the fourth index value. 19. The method as recited in claim 17, wherein the third index value is different than the fourth index value. 20. The method as recited in claim 11, wherein the first index value is different than the second index value, and wherein the third index value is different than the fourth index value. 21. An integrated circuit, comprising: a first cell configured to provide a logic function, the first cell including a gate level that includes a first number of linear-shaped gate level conductive structures, each of the first number of linear-shaped gate level conductive structures oriented to extend lengthwise in a first direction across an underlying substrate, wherein at least one of the first number of linear-shaped gate level conductive structures is positioned closest to a left boundary of the first cell and is separated from the left boundary of the first cell by a first distance as measured in a second direction perpendicular to the first direction, wherein the left boundary of the first cell is oriented in the first direction;a second cell configured to provide a logic function, the second cell including a gate level that includes a second number of linear-shaped gate level conductive structures, each of the second number of linear-shaped gate level conductive structures oriented to extend lengthwise in the first direction across the underlying substrate, wherein at least one of the second number of linear-shaped gate level conductive structures is positioned closest to a left boundary of the second cell and is separated from the left boundary of the second cell by a second distance as measured in the second direction that is different than the first distance as measured in the second direction, wherein the left boundary of the second cell is oriented in the first direction and overlies a right boundary of the first cell, wherein the right boundary of the first cell is oriented in the first direction,wherein both the first number of linear-shaped gate level conductive structures of the first cell and the second number of linear-shaped gate level conductive structures of the second cell are positioned in accordance with a fixed pitch such that a distance measured in the second direction between lengthwise-oriented centerlines of any two of the first and second numbers of linearshaped gate level conductive structures is an integer multiple of the fixed pitch. 22. The integrated circuit as recited in claim 21, wherein the logic function of the first cell is the same as the logic function of the second cell. 23. The integrated circuit as recited in claim 21, wherein the logic function of the first cell is different than the logic function of the second cell. 24. The integrated circuit as recited in claim 21, wherein an overall size of the first cell as measured in the second direction is substantially equal to an overall size the second cell as measured in the second direction. 25. The integrated circuit as recited in claim 21, wherein an overall size of the first cell as measured in the second direction is different than an overall size the second cell as measured in the second direction. 26. The integrated circuit as recited in claim 21, wherein the first cell includes an interconnect level formed at a location vertically positioned above the gate level, wherein the interconnect level includes a first number of linear-shaped interconnect level conductive structures, each of the first number of linear-shaped interconnect level conductive structures oriented to extend lengthwise in the first direction, wherein at least one of the first number of linear-shaped interconnect level conductive structures is positioned closest to a left boundary of the first cell and is separated from the lefi boundary of the first cell by a third distance as measured in the second direction, wherein the second includes an interconnect level that includes a second number of linear-shaped interconnect level conductive structures, each of the second number of linear-shaped interconnect level conductive structures oriented to extend lengthwise in the first direction, wherein at least one of the second number of linear-shaped interconnect level conductive structures is positioned closest to a left boundary of the second cell and is separated from the left boundary of the second cell by a fourth distance as measured in the second direction,wherein the fixed pitch for positioning of the first number of linear-shaped gate level conductive structures of the first cell and the second number of linear-shaped gate level conductive structures of the second cell is a first fixed pitch,wherein both the first number of linear-shaped interconnect level conductive structures of the first cell and the second number of linear-shaped interconnect level conductive structures of the second cell are positioned in accordance with a second fixed pitch such that a distance measured in the second direction between lengthwise-oriented centerlines of any two of the first and second numbers of linear-shaped interconnect level conductive structures is an integer multiple of the second fixed pitch,wherein the second fixed pitch is different than the first fixed pitch, and wherein the second fixed pitch is equal to the first fixed pitch multiplied by a ratio of integer values. 27. The integrated circuit as recited in claim 26, wherein the fourth distance as measured in the second direction is different than the third distance as measured in the second direction. 28. The integrated circuit as recited in claim 26, wherein the third distance as measured in the second direction is substantially equal to the first distance as measured in the second direction, and wherein the fourth distance as measured in the second direction is substantially equal to the second distance as measured in the second direction. 29. The integrated circuit as recited in claim 26, wherein the third distance as measured in the second direction is substantially equal to the first distance as measured in the second direction, and wherein the fourth distance as measured in the second direction is different than the second distance as measured in the second direction. 30. The integrated circuit as recited in claim 26, wherein the third distance as measured in the second direction is different than the first distance as measured in the second direction, and wherein the fourth distance as measured in the second direction is different than the second distance as measured in the second direction.
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