System and method for selectively coupled parasitic compensation for input referred voltage offset in electronic circuit
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-017/16
H03K-017/14
출원번호
US-0829070
(2015-08-18)
등록번호
US-9490795
(2016-11-08)
발명자
/ 주소
Naviasky, Eric
Ilhan, Ali Ulas
출원인 / 주소
Cadence Design Systems, Inc.
대리인 / 주소
Rosenberg, Klein & Lee
인용정보
피인용 횟수 :
0인용 특허 :
2
초록▼
A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampli
A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampling nodes defined by the input stage. The isolation node is configured to form first and second parasitic capacitances respectively with the control and sampling nodes during system operation. An offset switch is coupled to the isolation node and selectively set between first and second switching states. The offset switch selectively either maintains or interrupts a series coupling of the first and second parasitic capacitances between the control and sampling nodes; and, the sampling node is thereby adaptively adjusted in voltage by a predetermined portion of a control signal applied to the control node.
대표청구항▼
1. A system for selectively coupled parasitic compensation for input referred voltage offset in an electronic circuit, comprising: (a) at least one input stage for the electronic circuit, each said input stage including: a sampling switch controlled by a periodic control signal applied thereto at a
1. A system for selectively coupled parasitic compensation for input referred voltage offset in an electronic circuit, comprising: (a) at least one input stage for the electronic circuit, each said input stage including: a sampling switch controlled by a periodic control signal applied thereto at a control node to selectively pass an input signal to a sampling node; and,a hold capacitance element coupled between said sampling node and a voltage reference node; and,(b) at least one compensation cell coupled to each said input stage, said compensation cell including: an isolation node disposed in spaced manner from said control and sampling nodes, said isolation node configured to form first and second parasitic capacitance elements respectively with said control and sampling nodes during system operation; and,an offset switch coupled to said isolation node and selectively set between first and second switching states;wherein said offset switch in said first switching state maintains a series coupling of the first and second parasitic capacitance elements between said control and sampling nodes, said sampling node being thereby adaptively adjusted in voltage by a predetermined portion of the control signal; and, said offset switch in said second switching state coupling each of the first and second parasitic capacitance elements to said voltage reference node to interrupt the series coupling thereof. 2. The system as recited in claim 1, comprising at least two differentially paired input stages coupled to respective sampling nodes. 3. The system as recited in claim 1, wherein said control signal is a digital clock signal, and said sampling switch of said input stage includes at least one P-channel MOSFET device. 4. The system as recited in claim 1, wherein said voltage reference node is coupled to an electrically grounded portion of the system. 5. The system as recited in claim 1, comprising a plurality of said compensation cells for each said input stage, said compensation cells being enabled in different combinations by selectively setting said offset switches thereof to programmably adjust said sampling node in voltage by a corresponding portion of the control signal. 6. The system as recited in claim 1, wherein said isolation node of said compensation cell is defined by at least one metallic trace formed on a first integrated circuit substrate in predetermined geometric configuration and arrangement with respect to said control and sampling nodes. 7. The system as recited in claim 6, wherein said isolation node includes: a set of first metallic traces arranged in substantially parallel mutual arrangement and interconnected by at least one transverse metallic trace; and,a set of second metallic traces arranged in substantially parallel mutual arrangement each disposed in spaced manner from said first metallic traces;wherein said offset switch is interconnected to said first metallic traces. 8. The system as recited in claim 7, wherein: said control node is defined by at least one metallic trace formed on a second integrated circuit substrate offset in circuit level from said first integrated circuit substrate;said sampling node is defined by at least one metallic trace formed on the said first integrated circuit level substrate substantially in parallel to said transverse metallic trace of said isolation node; and,the first parasitic capacitance element is formed between said first and second metallic traces of said isolation node and said metallic trace of said control node, said second parasitic capacitance element being formed between said transverse metallic trace of said isolation node and said metallic trace of said sampling node. 9. The system as recited in claim 8, wherein said first metallic traces of said isolation node are disposed in interposed relation to said second metallic traces thereof. 10. A system for programmable parasitic cancellation of input referred voltage offset in a printed electronic circuit having a predetermined layout of devices interconnected by nets routed on at least one circuit substrate, comprising: (a) at least one input stage for the printed electronic circuit, each said input stage including: a sampling switch controlled by a periodic clock signal applied thereto at a control node to selectively pass an input signal to a sampling node; and,a hold capacitance element coupled between said sampling node and a voltage reference node; and,(b) a plurality of compensation cells coupled to each said input stage, each said compensation cell including: an isolation node disposed in spaced manner from said control and sampling nodes, said isolation node configured to form first and second parasitic capacitance elements respectively with said control and sampling nodes during system operation, said isolation node being defined by at least one metallic trace formed on a first printed circuit substrate in predetermined geometric configuration and arrangement with respect to said control and sampling nodes; and,an offset switch coupled to said isolation node and selectively configured between first and second switching states, said offset switch in said first switching state maintaining a series coupling of the first and second parasitic capacitance elements between said control and sampling nodes, said sampling node being thereby adaptively adjusted in voltage by a predetermined portion of the clock signal, said offset switch in said second switching state coupling each of the first and second parasitic capacitance elements to said voltage reference node to interrupt the series coupling thereof;wherein said compensation cells being enabled in different combinations by selectively configuring said offset switches thereof to programmably adjust said sampling node in voltage by a corresponding portion of the clock signal. 11. The system as recited in claim 10, wherein said voltage reference node is coupled to an electrically grounded portion of the system. 12. The system as recited in claim 11, wherein said isolation node includes: a set of first metallic traces arranged in substantially parallel mutual arrangement and interconnected by at least one transverse metallic trace; and,a set of second metallic traces arranged in substantially parallel mutual arrangement each disposed in spaced manner from said first metallic traces;wherein said offset switch is interconnected to said first metallic traces. 13. The system as recited in claim 12, wherein said first metallic traces of said isolation node are disposed in interposed relation to said second metallic traces thereof. 14. The system as recited in claim 13, wherein: said control node is defined by at least one metallic trace formed on a second printed circuit substrate offset in circuit level from said first printed circuit substrate;said sampling node is defined by at least one metallic trace formed on the said first printed circuit level substrate substantially in parallel to said transverse metallic trace of said isolation node; and,the first parasitic capacitance element is formed between said first and second metallic traces of said isolation node and said metallic trace of said control node, said second parasitic capacitance element being formed between said transverse metallic trace of said isolation node and said metallic trace of said sampling node. 15. The system as recited in claim 14, wherein said clock signal is a digital clock signal, and said sampling switch of said input stage includes at least one P-channel MOSFET device. 16. The system as recited in claim 15, comprising at least two differentially paired input stages coupled to respective sampling nodes. 17. A method for selectively coupled parasitic compensation of input referred voltage distortion in an electronic circuit, comprising: establishing at least one input stage for the electronic circuit, each said input stage including a sampling switch coupled to a control node and a hold capacitance element coupled between a sampling node and a voltage reference node;establishing an isolation node to be disposed in spaced manner from each of said control and sampling nodes;geometrically configuring and arranging said isolation node to form during system operation a first parasitic capacitance element with said control node and a second parasitic capacitance element with said sampling node; and,establishing an offset switch coupled to said isolation node, said offset switch being selectively configured between first and second switching states to form a compensation cell for said input stage;applying a periodic clock signal at said control node to actuate said sampling switch for selectively passing an input signal to said sampling node;selectively setting said offset switch to said first switching state to maintain a series coupling of the first and second parasitic capacitance elements between said control and sampling nodes, whereby said sampling node is adaptively adjusted in voltage by a predetermined portion of the clock signal; and,alternatively actuating said offset switch to said second switching state to couple each of the first and second parasitic capacitance elements to said voltage reference node and thereby interrupt the series coupling thereof. 18. The method as recited in claim 17, wherein said voltage reference node is coupled to an electrically grounded portion; a plurality of said compensation cells are established for each said input stage; and, said compensation cells are enabled in different combinations by selectively setting said offset switches thereof to programmably adjust said sampling node in voltage by a corresponding portion of the clock signal. 19. The method as recited in claim 17, wherein said isolation node of said compensation cell is defined by printing at least one metallic trace on a first integrated circuit substrate in predetermined geometric configuration and arrangement with respect to said control and sampling nodes by executing an electromagnetic field solver. 20. The method as recited in claim 19, wherein: said isolation node is configured to include: a set of first metallic traces arranged in substantially parallel mutual arrangement and interconnected by at least one transverse metallic trace; and,a set of second metallic traces arranged in substantially parallel mutual arrangement each disposed in spaced manner from said first metallic traces;said offset switch is interconnected to said first metallic traces;said control node is defined by printing at least one metallic trace on a second integrated circuit substrate offset in circuit level from said first integrated circuit substrate;said sampling node is defined by printing at least one metallic trace on the said first integrated circuit level substrate substantially in parallel to said transverse metallic trace of said isolation node; and,the first parasitic capacitance element is formed between said first and second metallic traces of said isolation node and said metallic trace of said control node, said second parasitic capacitance element being formed between said transverse metallic trace of said isolation node and said metallic trace of said sampling node.
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이 특허에 인용된 특허 (2)
Sander,Rainald, Circuit arrangement having a power transistor and a drive circuit for the power transistor.
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