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Provided is a logic configuration method for a semiconductor device having a plurality of memory units provided with a plurality of memory cells; each memory unit is configured to store truth table data in the memory cells thereof, the truth table data being for outputting a logic value in response

Provided is a logic configuration method for a semiconductor device having a plurality of memory units provided with a plurality of memory cells; each memory unit is configured to store truth table data in the memory cells thereof, the truth table data being for outputting a logic value in response to an address input, and to operate as a logic circuit; the memory units have n (where n is 2 or a higher integer) times two pairs of an input line and an output line; the n times two output lines from one memory unit among the memory units are connected to the n input lines of two other memory units; and the logic configuration method generates, on the basis of the circuit description describing the circuit configuration, a netlist having circuit connection information, extracts a logic cone from the netlist, and generates truth table data for the plurality of memory units, which constitute the logic cone, in the memory unit stage number corresponding to the number obtained by dividing the number of input lines to the logic cone by n/2.

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1. A logic configuration method for a reconfigurable semiconductor device having a plurality of memory units each including a plurality of memory cells that store data, wherein the memory units are configured to operate as logic circuits by storing, in the memory cells therein, truth table data that

1. A logic configuration method for a reconfigurable semiconductor device having a plurality of memory units each including a plurality of memory cells that store data, wherein the memory units are configured to operate as logic circuits by storing, in the memory cells therein, truth table data that outputs logic values in response to address input,wherein the memory units each have at least 2×n input lines and output lines forming pairs, n being an integer of greater than or equal to 2,wherein the memory units are connected to each other by 2×n output lines from one memory unit being connected to an n number of input lines of two other memory units, andwherein the logic configuration method comprises: generating a netlist having circuit connective information on the basis of a circuit description that describes a circuit configuration to be implemented in the reconfigurable semiconductor device;extracting a logic cone that includes sequential logics from the netlist;determining the number of stages of memory units that are to be used to constitute the extracted logic cone on a basis of a quotient obtained by dividing a number of input lines to the extracted logic cone by n/2; andgenerating the truth table data for the memory units that constitute the extracted logic cone. 2. The logic configuration method according to claim 1, wherein the step of generating the netlist includes typecasting variable bits in a program coded in a high level language to a smaller bit size. 3. The logic configuration method according to claim 1, wherein the memory units are each connected to other memory units on one side and another side opposite to the one side, and have a plurality of memory cell units,wherein at least one of the plurality of memory cell units has a plurality of memory cells, and the memory cells store first truth table data for outputting a logic value from the one side and second truth table data for outputting a logic value from said another side in response to address input from the one side, andwherein the step of generating the truth table data includes generating the first truth table data and the second truth table data. 4. The logic configuration method according to claim 1, wherein the step of generating the netlist includes at least one of loop unrolling and parallelization in a program coded in a high level language. 5. The logic configuration method according to claim 1, further comprising: extracting a scannable sequential logic data set from the netlist and generating a scanned sequential logic data set;generating a first truth table data for writing to a first set among the plurality of memory cell units from the scanned sequential logic data set; andgenerating a second truth table data for writing to a second set among the plurality of memory cell units from a combinational logic circuit data set of the netlist. 6. The logic configuration method according to claim 1, wherein the semiconductor device has, in addition to the memory units, a plurality of logic units each having a sequential logic element, andwherein the logic configuration method further comprises: generating the netlist describing logic circuit data, sequential logic data, and connective information of the logic circuit data and the sequential logic data from the circuit description describing the circuit configuration; andallocating the logic circuit data and the sequential logic data respectively to the memory cells and the logic circuit elements from the generated netlist according to the connective information. 7. The logic configuration method according to claim 6, wherein the semiconductor device has switching elements on outer portions of the logic units, andwherein the logic configuration method further comprises: allocating connective information of the netlist to the switching elements. 8. The logic configuration method according to claim 6, wherein the memory cells of the memory units operate as connective elements when truth table data, configured to output to the memory units of other logic units an input value identified by an address, is written, andwherein the logic configuration method further comprises: allocating connective information of the netlist to the memory units. 9. The logic configuration method according to claim 6, wherein the sequential logic data is removed after generating the netlist, andwherein the logic circuit data is allocated to the memory cells, and then the sequential logic data is allocated to the logic circuit elements from the generated netlist in accordance with the connective information. 10. The logic configuration method according to claim 6, wherein the step of generating the netlist includes generating logic circuit data, sequential logic data, and a parallel-in/serial-out shift register including the logic circuit data. 11. The logic configuration method according to claim 6, wherein the sequential logic elements store data read from the memory units and are sequential logics that output the stored data in synchronization with a clock signal. 12. A logic configuration device that performs logic configuration for a semiconductor device having a plurality of memory units each including a plurality of memory cells that store data, wherein the semiconductor device is configured such that the memory units operate as logic circuits by storing, in the memory cells therein, truth table data that outputs logic values in response to address input,wherein the memory units each have at least 2×n input lines and output lines forming pairs, n being an integer of greater than or equal to 2,wherein the memory units are connected to each other by 2×n output lines from one memory unit being connected to an n number of input lines of two other memory units,wherein the logic configuration device comprises a processor, andwherein the processor is configured so as to generate a netlist having circuit connective information on the basis of a circuit description that describes a circuit configuration to be implemented in the semiconductor device;extract a logic cone that includes sequential logics from the netlist;determine the number of stages of memory units that are to be used to constitute the extracted logic cone on a basis of a quotient obtained by diving a number of input lines to the extracted logic cone by n/2; andgenerate the truth table data for the memory units that constitute the extracted logic cone. 13. The logic configuration device according to claim 12, wherein generation of the netlist includes typecasting variable bits in a program coded in a high level language to a smaller bit size. 14. The logic configuration device according to claim 12, wherein the memory units are each connected to other memory units on one side and another side opposite to the one side, and have a plurality of memory cell units,wherein at least one of the plurality of memory cell units has a plurality of memory cells, and the memory cells store first truth table data for outputting a logic value from the one side and second truth table data for outputting a logic value from said another side in response to address input from the one side, andwherein the generation of the truth table data includes generating the first truth table data and the second truth table data. 15. The logic configuration device according to claim 12, wherein the generation of the netlist includes at least one of loop unrolling and parallelization in a program coded in a high level language. 16. The logic configuration device according to claim 12, wherein the processor is configured so as to extract a scannable sequential logic data set from the netlist and generate a scanned sequential logic data set;generate a first truth table data set for writing to a first set among the plurality of memory cell units from the scanned sequential logic data set; andgenerate a second truth table data set for writing to a second set among the plurality of memory cell units from a combinational logic circuit data set of the netlist. 17. The logic configuration device according to claim 12, wherein the semiconductor device has, in addition to the memory units, a plurality of logic units having sequential logic elements,wherein the processor generates the netlist describing logic circuit data, sequential logic data, and connective information of the logic circuit data and the sequential logic data from the circuit description describing the circuit configuration; andallocates the logic circuit data and the sequential logic data respectively to the memory cells and the logic circuit elements from the generated netlist according to the connective information. 18. The logic configuration device according to claim 17, wherein the semiconductor device has switching elements on outer portions of the logic units, andwherein the logic configuration device further comprises: allocating connective information of the netlist to the switching elements. 19. The logic configuration device according to claim 17, wherein the memory cells of the memory units operate as connective elements when truth table data, configured to output to the memory units of other logic units an input value identified by an address, is written, andwherein the processor is configured so as to allocate connective information of the netlist to the memory units. 20. The logic configuration device according to claim 17, wherein the processor is configured so as to remove the sequential logic data after generating the netlist, andallocate the logic circuit data to the memory cells, and then allocate the sequential logic data to the logic circuit elements from the generated netlist in accordance with the connective information. 21. The logic configuration device according to claim 17, wherein generating the netlist includes generating logic circuit data, sequential logic data, and a parallel-in/serial-out shift register including the logic circuit data. 22. The logic configuration device according to claim 17, wherein the sequential logic elements store data read from the memory units and are sequential logics that output the stored data in synchronization with a clock signal. 23. A non-transitory storage medium that stores a program executable by a processor, the program being for performing logic configuration for a semiconductor device having a plurality of memory units each including a plurality of memory cells that store data, wherein the semiconductor device is configured such that the memory units operate as logic circuits by storing, in the memory cells therein, truth table data that outputs logic values in response to address input,wherein the memory units each have at least 2×n input lines and output lines forming pairs, n being an integer of greater than or equal to 2,wherein the memory units are connected to each other by 2×n output lines from one memory unit being connected to an n number of input lines of two other memory units, andwherein said program causes the processor to perform the following: generating a netlist having circuit connective information on the basis of a circuit description that describes a circuit configuration to be implemented in the reconfigurable semiconductor device;extracting a logic cone that includes sequential logics from the netlist;determining the number of stages of memory units that are to be used to constitute the extracted logic cone on a basis of a quotient obtained by dividing a number of input lines to the extracted logic cone by n/2; andgenerating the truth table data for the memory units that constitute the extracted logic cone. 24. The non-transitory storage medium according to claim 23, wherein generation of the netlist includes typecasting variable bits in a program coded in a high level language to a smaller bit size. 25. The non-transitory storage medium according to claim 23, wherein the memory units are each connected to other memory units on one side and another side opposite to the one side, and have a plurality of memory cell units,wherein at least one of the plurality of memory cell units has a plurality of memory cells, and the memory cells store first truth table data for outputting a logic value from the one side and second truth table data for outputting a logic value from said another side in response to address input from the one side, andwherein the process of generating the truth table data includes a process of generating the first truth table data and the second truth table data. 26. The non-transitory storage medium according to claim 23, wherein the generation of the netlist includes at least one of loop unrolling and parallelization in a program coded in a high level language. 27. The non-transitory storage medium according to claim 23, wherein said program causes the processor to perform the following: extracting a scannable sequential logic data set from the netlist and generating a scanned sequential logic data set;generating a first truth table data set for writing to a first set among the plurality of memory cell units from the scanned sequential logic data set; andgenerating a second truth table data set for writing to a second set among the plurality of memory cell units from a combinational logic circuit data set of the netlist. 28. The non-transitory storage medium according to claim 23, wherein the semiconductor device has, in addition to the memory units, a plurality of logic units having sequential logic elements,wherein said program causes the processor to perform the following: generating the netlist describing logic circuit data, sequential logic data, and connective information of the logic circuit data and the sequential logic data from the circuit description describing the circuit configuration; andallocating the logic circuit data and the sequential logic data respectively to the memory cells and the logic circuit elements from the generated netlist in accordance with the connective information. 29. The non-transitory storage medium according to claim 28, wherein the semiconductor device has switching elements on outer portions of the logic units, andwherein said program causes the processor to execute a process of allocating connective information of the netlist to the switching elements. 30. The non-transitory storage medium according to claim 28, wherein the memory cells of the memory units operate as connective elements when truth table data, configured to output to the memory units of other logic units an input value identified by an address, is written, andwherein the processor executes a process of allocating connective information of the netlist to the memory units. 31. The non-transitory storage medium according to claim 28, wherein said program causes the processor to perform the following: removing the sequential logic data after generating the netlist, andallocating the logic circuit data to the memory cells, and then allocating the sequential logic data to the logic circuit elements from the generated netlist in accordance with the connective information. 32. The non-transitory storage medium according to claim 28, wherein generation of the netlist includes a process of generating logic circuit data, sequential logic data, and a parallel-in/serial-out shift register including the logic circuit data. 33. The non-transitory storage medium according to claim 23, wherein the sequential logic elements store data read from the memory units and are sequential logics that output the stored data in synchronization with a clock signal.