초록 ▼

A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmeti

A system and method for high-speed, low-power cryogenic computing are presented, comprising ultrafast energy-efficient RSFQ superconducting computing circuits, and hybrid magnetic/superconducting memory arrays and interface circuits, operating together in the same cryogenic environment. An arithmetic logic unit and register file with an ultrafast asynchronous wave-pipelined datapath is also provided. The superconducting circuits may comprise inductive elements fabricated using both a high-inductance layer and a low-inductance layer. The memory cells may comprise superconducting tunnel junctions that incorporate magnetic layers. Alternatively, the memory cells may comprise superconducting spin transfer magnetic devices (such as orthogonal spin transfer and spin-Hall effect devices). Together, these technologies may enable the production of an advanced superconducting computer that operates at clock speeds up to 100 GHz.

대표청구항 ▼

1. A cryogenic computing system, comprising: a high-speed superconducting digital processor, configured to operate at cryogenic temperatures at a clock rate of at least 20 GHz, comprising an asynchronous wave-pipelined datapath;an array of memory cells, comprising a plurality of serially-biased modu

1. A cryogenic computing system, comprising: a high-speed superconducting digital processor, configured to operate at cryogenic temperatures at a clock rate of at least 20 GHz, comprising an asynchronous wave-pipelined datapath;an array of memory cells, comprising a plurality of serially-biased modular superconducting circuits having a plurality of isolated ground planes, configured to operate at cryogenic temperatures; andsuperconducting interface circuits configured to communicate between the array of memory cells and the processor. 2. The cryogenic computing system of claim 1, wherein the digital processor comprises energy-efficient rapid-single-flux-quantum logic. 3. The cryogenic computing system of claim 1, wherein both the digital processor and the array of memory cells are configured to operate at cryogenic temperatures less than 10 K. 4. The cryogenic computing system of claim 1, wherein the array of memory cells comprises a plurality of memory cells, each comprising a Josephson junction having a Josephson junction barrier having a thin magnetic layer. 5. The cryogenic computing system of claim 4, wherein the plurality of memory cells are read out using ballistic single-flux-quantum pulses. 6. The cryogenic computing system of claim 4, wherein each memory cell of the array of memory cells is selected using a three-terminal superconducting device. 7. The cryogenic computing system of claim 1, wherein the array of memory cells and the digital processor are each provided as separate chips on respective multi-chip modules (MCMs), further comprising a high-speed parallel communication bus between the respective MCMs. 8. The cryogenic computing system of claim 7, wherein the high-speed parallel communication bus communicates using single-flux-quanta on superconducting transmission lines. 9. The cryogenic computing system of claim 7, further comprising a receiver having a clock recovery circuit interfaced to the high speed parallel communication bus. 10. The cryogenic computing system of claim 7, further comprising a room-temperature controller configured to control at least the high-speed superconducting digital processor. 11. The cryogenic computing system of claim 10, where the high-speed superconducting digital processor and the room temperature controller communicate via serial communication at a substantially lower rate than the high speed parallel communication bus. 12. A superconducting computer configured to operate at superconducting temperatures, comprising: a processor integrated circuit comprising energy-efficient superconducting rapid-single-flux-quantum logic and superconducting memory register cells, having ultrafast wave-pipelining in both the energy-efficient superconducting rapid-single-flux-quantum logic and the memory register cells, comprising a plurality of serially biased modular superconducting circuits;a cryogenic random access memory array integrated circuit comprising a plurality of memory cells each having superconducting Josephson junctions; andat least one superconducting interface circuit disposed between the processor integrated circuit and the cryogenic random access memory array integrated circuit,wherein the processor integrated circuit and cryogenic random access memory array integrated circuit are packaged on at least one multi-chip module (MCM) configured to permit ultrafast data transfer between the processor integrated circuit and the cryogenic random access memory array integrated circuit. 13. The superconducting computer of claim 12, further comprising a cryogenic system configured to maintain the processor integrated circuit and the cryogenic random access memory array integrated circuit at cryogenic temperatures suitable for operation of superconducting digital logic elements. 14. The superconducting computer of claim 12, wherein both the processor integrated circuit and the cryogenic random access memory array integrated circuit are configured to operate at cryogenic temperatures less than 10 K. 15. The superconducting computer of claim 12, wherein the cryogenic random access memory array integrated circuit comprises a plurality of memory cells, each memory cell comprising a Josephson junction having a Josephson junction barrier having a thin magnetic layer. 16. The superconducting computer of claim 12, further comprising: a high-speed parallel communication bus configured to communicate data between the respective MCMs with using single-flux-quanta on superconducting transmission lines, anda receiver comprising a clock recovery circuit, configured to recover a clock associated with communication of the data through the high speed parallel communication bus from the communicated single-flux-quanta. 17. A processing method, comprising: cooling a cryogenic computing system within a temperature range at which low temperature superconducting materials are superconductive, the cryogenic computing system comprising: a superconducting digital processor comprising an asynchronous wave-pipelined datapath, an array of memory cells, comprising a plurality of serially-biased modular superconducting circuits having a plurality of isolated ground planes, and superconducting interface circuits configured to communicate between the array of memory cells and the superconducting digital processor;transforming at least one digital datum by the superconducting digital processor;transferring the transformed at least one digital datum through the superconducting interface circuits; andstoring the transformed at least one digital datum in the array of memory cells. 18. The processing method of claim 17, wherein the superconducting digital processor comprises energy-efficient rapid-single-flux-quantum logic. 19. The processing method of claim 17, wherein both the superconducting digital processor and the array of memory cells are configured to operate at temperatures less than 10 K, further comprising cooling the superconducting digital processor and the array of memory cells to a temperature below 10 K. 20. The processing method of claim 17, wherein the array of memory cells comprises a plurality of memory cells, each memory cell comprising at least one Josephson junction having a Josephson junction barrier having a thin magnetic layer. 21. The processing method of claim 20, further comprising wherein reading out the plurality of memory cells using ballistic single-flux-quantum pulses. 22. The processing method of claim 20, further comprising selecting a memory cell from the array of memory cells using a respective three-terminal superconducting device associated with the respective selected memory cell. 23. The processing method of claim 17, wherein the array of memory cells and the superconducting digital processor are each provided as separate chips on respective multi-chip modules (MCMs), further comprising: communicating data between the respective MCMs with a high-speed parallel communication bus using single-flux-quanta on superconducting transmission lines, andrecovering a clock associated with the data communication using a receiver having a clock recovery circuit. 24. The processing method of claim 17, further comprising controlling at least the superconducting digital processor with a room-temperature controller.