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An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region whic

An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.

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1. An apparatus including an electrostatic discharge protection device comprising: a semiconductor well;a collector region doped with a first conductivity type, wherein the collector region is positioned inside of the well;a base region separated from the collector region and doped with a second con

1. An apparatus including an electrostatic discharge protection device comprising: a semiconductor well;a collector region doped with a first conductivity type, wherein the collector region is positioned inside of the well;a base region separated from the collector region and doped with a second conductivity type opposite the first conductivity type, wherein the base region is positioned inside of the well;an emitter region located within the base region and doped with the first conductivity type, wherein the emitter region is positioned inside of the well;a buried region of semiconductor vertically aligned and spaced apart from the base region and doped with the second conductivity type, wherein the buried region is positioned inside of the well;wherein the well, the base region and the buried region are doped with the second conductivity type, and wherein the base region and the buried region have a higher doping concentration of the second conductivity type than the well,wherein the collector region, the base region, and the emitter region are configured to operate as a bipolar transistor,wherein the bipolar transistor comprises a horizontal bipolar transistor, and wherein the buried region inhibits formation of a vertical bipolar transistor,wherein the apparatus is configured such that a width of the separation between the collector and base regions establishes a trigger voltage to cause the electrostatic discharge protection device to become conducting; andwherein the apparatus is configured such that a spatial parameter of the base region establishes a holding voltage of the electrostatic discharge protection device. 2. The apparatus as claimed in claim 1, further comprising a non-protective transistor, the non-protective transistor including doped regions, wherein at least one of the doped regions of the non-protective transistor and at least one of the collector, base, or emitter regions are formed by a common dopant dose. 3. The apparatus as claimed in claim 2, wherein the non-protective transistor comprises a metal-oxide-semiconductor field effect transistor (MOSFET). 4. The apparatus as claimed in claim 1, in which the spatial parameter is one of a width of the base region, an area of the base region or a volume of the base region. 5. The apparatus as claimed in claim 4, in which the spatial parameter in part controls a current gain in the bipolar transistor, which in turn changes the holding voltage. 6. The apparatus as claimed in claim 1, in which the electrostatic discharge protection device is formed in an integrated circuit and the collector and base regions are isolated from other devices formed in a silicon substrate by one of: (1) a doped region of the substrate around the electrostatic discharge protection device forming a reverse biased junction; or(2) insulating regions around the electrostatic discharge protection device. 7. The apparatus as claimed in claim 1, in which the collector and emitter regions are doped with donor impurities such that the bipolar transistor is an NPN transistor. 8. The apparatus as claimed in claim 1, in which the trigger voltage is controlled in part by a distance between an edge of a collector region and an edge of a base region of the bipolar transistor. 9. The apparatus as claimed in claim 8, in which the holding voltage is controlled in part by a width of the base region. 10. The apparatus as claimed in claim 1, further including a resistor interconnecting the base and the emitter region of the bipolar transistor. 11. The apparatus as claimed in claim 1, wherein the electrostatic discharge device is a unidirectional protection device, wherein the collector region of the bipolar transistor is connected to a terminal to be protected, and the emitter region is connected to a supply rail of an integrated circuit including the unidirectional protection device. 12. The apparatus as claimed in claim 1, forming a bi-directional electrostatic discharge protection device comprising first and second electrostatic discharge protection devices as claimed in claim 1 arranged in series. 13. The apparatus as claimed in claim 12, in which the collector regions of the first and second electrostatic discharge protection devices are connected to each other, the base and the emitter region of the first device are connected to a terminal to be protected, and the base and the emitter region of the second electrostatic discharge protection device is in current flow communication with a supply rail. 14. The apparatus as claimed in claim 1, further comprising a conductor connected to a supply rail and provided above the surface of or adjacent the bipolar transistor so as to act as a field plate. 15. The apparatus as claimed in claim 1, in which the electrostatic discharge protection device is formed in an integrated circuit. 16. The apparatus as claimed in claim 1, wherein the well is p-type, wherein the collector region is n-type, wherein the base region is p-type, wherein the emitter region is n-type, and wherein the buried region is p-type. 17. The apparatus as claimed in claim 1, further comprising a substrate, wherein the well is isolated from the substrate by a dielectric region. 18. The apparatus as claimed in claim 17, wherein the base region surrounds the emitter region when viewed from above the substrate, and wherein the collector region surrounds the base region when viewed from above the substrate.