Simple and robust digital code tracking loop for wireless communication systems
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04B-001/7085
H04B-001/7115
H04B-001/707
H04B-001/7117
출원번호
US-0544665
(2012-07-09)
등록번호
US-9525455
(2016-12-20)
발명자
/ 주소
Li, Bin
출원인 / 주소
InterDigital Technology Corporation
대리인 / 주소
Volpe and Koenig, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
40
초록▼
A simple and robust CTL is used for time tracking of multipath components of a spread spectrum signal transmitted over a wireless multipath fading channel. A digital code-tracking loop includes despreading early and late data samples by use of a pseudonoise sequence, an error signal output generated
A simple and robust CTL is used for time tracking of multipath components of a spread spectrum signal transmitted over a wireless multipath fading channel. A digital code-tracking loop includes despreading early and late data samples by use of a pseudonoise sequence, an error signal output generated by the despreading, and adjustment for a plurality of on-time, early and late samples, a data rate of a control signal provided as a fractional proportion of a data rate of error signals.
대표청구항▼
1. A digital code-tracking loop comprising: a despreader for despreading early and late data samples by use of a pseudo noise sequence;a detector configured to generate an error signal for each set of early and late data samples coherently, wherein the error signal is generated coherently on a condi
1. A digital code-tracking loop comprising: a despreader for despreading early and late data samples by use of a pseudo noise sequence;a detector configured to generate an error signal for each set of early and late data samples coherently, wherein the error signal is generated coherently on a condition that a transmitted signal is estimated;an interpolator for generating the early and late samples of a received signal, wherein the interpolator is adjusted by a control signal either forward or backward by a number samples, wherein the control signal adjusts at a fractional chip rate, where the control signal is generated according to a sign of a sum of a plurality of error signals from the detector;wherein generating the error signal coherently comprises estimating the transmitted signal by removing modulated data from the despread early samples and despread late samples according to: Se(k)a(k)* and Sl(k)a(k)*,wherein Se(k) is the despread early signal, Sl(k) is the despread late samples, and a(k)* equals the complex conjugate of the estimated transmitted samples; andthe error signal is calculated as: Er(k)=∑k=1N1Se(k)a(k)*2-∑k=1N1Sl(k)a(k)*2wherein N1 equals a number of despread early and late samples used to calculate the error signal. 2. The digital code-tracking loop of claim 1, wherein: the error signals provide timing tracking. 3. The digital code tracking loop of claim 2, wherein for every N samples, one sample provides an on-time synchronized sample, used for despreading, demodulation and rake combining, the code tracking loop tracking timing and selecting the on-time sample, where N>1. 4. The digital code tracking loop of claim 2, wherein: the received signal comprises a plurality of slots of a dedicated physical control channel including 10 symbols, the 10 symbols providing pilot, transmit power control and transport format combination indication (TFCI) bits; andthe code tracking loop is updated every 2 frames. 5. The digital code-tracking loop of claim 1, wherein the adjustment provides time tracking of multipath component of direct sequence spread spectrum signal over a wireless multipath fading channel. 6. A radio transmission controller implementing a digital code-tracking loop, the radio transmission controller comprising: a despreading circuit for despreading sets of early and late data samples by use of a pseudo noise sequence;a detector circuit providing an error signal for each set of early and late data samples coherently, wherein the error signal is generated coherently on a condition that a transmitted signal is estimated;a control circuit providing a control signal; anda interpolator circuit providing the sets of early and late samples based on a received signal, wherein the interpolator circuit is adjusted by the control signal either forward or backward by a number of samples, wherein the control signal adjusts at a fractional chip rate, where the control signal is generated according to a sign of a sum of a plurality of error signals from the detector;wherein generating the error signal coherently comprises estimating the transmitted signal by removing modulated data from the despread early samples and despread late samples according to: Se(k)a(k)* and Sl(k)a(k)*,wherein Se(k) is of the despread early signal, Sl(k) is the despread late samples, and a(k)* equals the complex conjugate of the estimated transmitted samples; andthe error signal is calculated as: Er(k)=∑k=1N1Se(k)a(k)*2-∑k=1N1Sl(k)a(k)*2wherein N1 equals a number of despread early and late samples used to calculate the error signal. 7. The radio transmission controller of claim 6, wherein the detector circuit provides timing tracking. 8. The radio transmission controller of claim 7, wherein for every N samples, one sample provides an on-time synchronized sample, used for despreading, demodulation and rake combining, the code tracking loop tracking timing and selecting the on-time sample, where N>1. 9. The radio transmission controller of claim 7, wherein the received signal comprises: a plurality of slots of a dedicated physical control channel including 10 symbols, the 10 symbols providing pilot, transmit power control and transport format combination indication (TFCI) bits; andthe code tracking loop is updated every 2 frames. 10. The radio transmission controller of claim 6, wherein the adjustment provides time tracking of multipath component of direct sequence spread spectrum signal over a wireless multipath fading channel. 11. The radio transmission controller of claim 6, wherein the detector circuit comprises a joint error signal calculator circuit providing the error signal. 12. The radio transmission controller of claim 11, wherein the joint error signal calculator provides an indication of a relative delay τ between two multipath components of a composite signal. 13. The radio transmission controller of claim 12, wherein the relative delay τ provides an indication of a delay for signal interference calculation.
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