Switching element, semiconductor device, and semiconductor device manufacturing method
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/06
H01L-021/66
H01L-027/10
H01L-029/78
H01L-029/16
H01L-029/20
H01L-021/52
H01L-021/8234
H01L-023/522
H01L-023/528
H01L-049/02
H01L-029/423
H01L-029/739
출원번호
US-0897797
(2013-09-09)
등록번호
US-9553084
(2017-01-24)
국제출원번호
PCT/JP2013/074284
(2013-09-09)
국제공개번호
WO2015/033476
(2015-03-12)
발명자
/ 주소
Hasegawa, Shigeru
Morishita, Kazuhiro
Kitani, Takeshi
출원인 / 주소
Mitsubishi Electric Corporation
대리인 / 주소
Studebaker & Brackett PC
인용정보
피인용 횟수 :
0인용 특허 :
1
초록▼
According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to eac
According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element.
대표청구항▼
1. A switching element comprising: a substrate;a first gate pad formed on the substrate;a second gate pad formed on the substrate;a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other; anda cell region formed
1. A switching element comprising: a substrate;a first gate pad formed on the substrate;a second gate pad formed on the substrate;a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other; anda cell region formed on the substrate and connected to the first gate pad,wherein a wire can be fixed to the first gate pad and the second gate pad. 2. The switching element according to claim 1, further comprising: a third gate pad formed on the substrate; anda second resistor portion formed on the substrate, the second resistor portion connecting the second gate pad and the third gate pad to each other. 3. The switching element according to claim 1, further comprising: a first additional gate pad formed on the substrate; anda first additional resistor portion formed on the substrate, the first additional resistor portion connecting the first gate pad and the first additional gate pad to each other. 4. The switching element according to claim 3, further comprising: a second additional gate pad formed on the substrate; anda second additional resistor portion formed on the substrate, the second additional resistor portion connecting the second additional gate pad and the first additional gate pad to each other. 5. The switching element according to claim 1, wherein the first gate pad is outside the cell region, and the switching element further comprises a connecting part formed on the substrate, the connecting part connecting the first gate pad and the cell region to each other. 6. The switching element according to claim 5, wherein the connecting part is formed of a piece of wiring. 7. The switching element according to claim 5, wherein the connecting part is formed of a resistor portion. 8. The switching element according to claim 1, further comprising: a plurality of gate pads including the first gate pad and the second gate pad; anda plurality of resistor portions including the first resistor portion, the plurality of resistor portions connecting the plurality of gate pads so that all the plurality of gate pads are electrically connected to the first gate pad,wherein the plurality of gate pads are formed so as to surround the cell region. 9. The switching element according to claim 1, wherein the first gate pad is formed in the cell region. 10. The switching element according to claim 1, wherein the substrate is formed of a wide-bandgap semiconductor. 11. The switching element according to claim 10, wherein the wide-bandgap semiconductor is silicon carbide, a gallium nitride-based material or diamond. 12. A semiconductor device comprising: a plurality of switching elements each including a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad; anda plurality of wires respectively connected to the first gate pads or the second gate pads of the plurality of switching elements, each of the plurality of wires being capable of supplying a control signal,wherein a wire can be fixed to the first gate pad and the second gate pad. 13. A method of manufacturing a semiconductor device, comprising: a step of manufacturing a switching element including a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad;a step of measuring the resistance value of the first resistor portion by setting probes to the first gate pad and the second gate pad; anda step of mounting the switching element in a module if the resistance value meets a standard, whereina wire can be fixed to the first gate pad and the second gate pad. 14. A method of manufacturing a semiconductor device, comprising: a step of manufacturing a plurality of switching elements each including a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad;a step of measuring the resistance value of the first resistor portion with respect to each of the plurality of switching elements by setting probes to the first gate pad and the second gate pad; anda step of selecting one of the plurality of switching elements having the resistance value within a desired range and mounting the selected switching element in one semiconductor device, whereina wire can be fixed to the first gate pad and the second gate pad.
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이 특허에 인용된 특허 (1)
Sakamoto Kozo (Hachiouji JPX) Yoshida Isao (Hinode-machi JPX) Otaka Shigeo (Takasaki JPX) Iijima Tetsuo (Maebashi JPX) Shono Harutora (Gunma-machi JPX) Uchid Ken (Higashiyamato JPX) Kobayashi Masayos, Insulated gate semiconductor device and driving circuit device and electronic system both using the same.
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