A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instru
A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.
대표청구항▼
1. A reconfigurable processor, comprising: a status register configured to store a status value;a control register configured to store pending information used to adjust a point in time for initiating a subsequent program by verifying whether an operation according to coarse grained architecture (CG
1. A reconfigurable processor, comprising: a status register configured to store a status value;a control register configured to store pending information used to adjust a point in time for initiating a subsequent program by verifying whether an operation according to coarse grained architecture (CGA) logic is terminated;a parallel processing scheduler configured to determine whether to execute very long instruction word (VLIW) logic and the CGA logic in a single execution mode or in a parallel mode based on the stored status value and pending information, and to schedule at least one of the VLIW logic and the CGA logic to be executed based on the determination;a VLIW register configured to store VLIW processed data according to the VLIW logic; anda CGA register configured to store CGA processed data according to the CGA logic,wherein the parallel processing scheduler is configured to: schedule processed data to be duplicated between the VLIW register and the CGA register in response to execution of each of the VLIW logic and the CGA logic, when the processor is operated in the single execution mode, andschedule processed data to be duplicated between the VLIW register and the CGA register after synchronizing of a termination point in time between the VLIW logic and the CGA logic, when the processor is operated in the parallel mode. 2. The reconfigurable processor of claim 1, wherein when the determination is to operate the processor in the single execution mode, the parallel processing scheduler is configured to schedule the VLIW logic and the CGA logic to be sequentially processed. 3. The reconfigurable processor of claim 2, wherein in scheduling the VLIW logic and the CGA logic to be sequentially processed, the parallel processing scheduler is configured to schedule the VLIW logic to be executed,schedule the VLIW processed data stored in the VLIW register to be duplicated to the CGA register in response to execution of the VLIW logic,schedule the CGA logic to be executed in response to termination of the VLIW logic, andschedule the CGA processed data stored in the CGA register to be duplicated to the VLIW register in response to execution of the CGA logic. 4. The reconfigurable processor of claim 1, wherein when the determination is to operate the processor in the parallel mode, the parallel processing scheduler is configured to schedule the VLIW logic and the CGA logic to be processed in parallel. 5. The reconfigurable processor of claim 4, wherein in scheduling the VLIW logic and the CGA logic to be processed in parallel, the parallel processing scheduler is configured to schedule termination of a previous CGA logic to be verified,schedule the VLIW processed data to be duplicated to the CGA register when the previous CGA logic is terminated, andschedule the VLIW logic and the CGA logic to be processed in parallel. 6. The reconfigurable processor of claim 5, wherein the parallel processing scheduler is configured to schedule the control register to be activated in response to execution of the CGA logic. 7. A reconfigurable processor, comprising: a status register configured to store a status value;a parallel processing scheduler configured to schedule at least one of very long instruction word (VLIW) logic and coarse grained architecture (CGA) logic to be used based on the stored status value;a VLIW register configured to store processed data according to the VLIW logic; anda CGA register configured to store processed data according to the CGA logic,wherein the parallel processing scheduler is configured to: schedule the processed data to be duplicated between the VLIW register and the CGA register in response to execution of each of the VLIW logic and the CGA logic, when the processor is operated in a single execution mode, andschedule the processed data to be duplicated between the VLIW register and the CGA register after synchronizing of a termination point in time between the VLIW logic and the CGA logic, when the processor is operated in a parallel mode. 8. The reconfigurable processor of claim 7, wherein the parallel processing scheduler is configured to schedule the VLIW logic and the CGA logic to be processed in parallel based on the stored status value. 9. The reconfigurable processor of claim 8, wherein the parallel processing scheduler is configured to schedule the VLIW logic and the CGA logic to be sequentially processed based on the stored status value. 10. The reconfigurable processor of claim 8, further comprising: a control register configured to store pending information used to adjust a point in time for initiating a subsequent program by verifying whether an operation according to the CGA logic is terminated. 11. The reconfigurable processor of claim 10, wherein the parallel processing scheduler is configured to verify whether the operation according to the CGA logic is terminated, and to duplicate a file stored in the VLIW register and to move the duplicated file to the CGA register when the operation according to the CGA logic is terminated. 12. The reconfigurable processor of claim 11, wherein when the file stored in the VLIW register is duplicated and moved to the CGA register, the parallel processing scheduler is configured to inform that the CGA logic is being executed by setting a value stored in the control register. 13. The reconfigurable processor of claim 12, wherein the parallel processing scheduler is configured to simultaneously execute the VLIW logic and the CGA logic after setting the value stored in the control register. 14. An operation method of a reconfigurable processor, the method comprising: storing, by a status register, a status value used to determine at least one execution mode in a processor;scheduling, by a parallel processing scheduler, at least one of very long instruction word (VLIW) logic and coarse grained architecture (CGA) logic to be used based on the stored status value;storing, by a VLIW register, processed data according to the VLIW logic; andstoring, by a CGA register, processed data according to the CGA logic,wherein the parallel processing scheduler is configured to: schedule the processed data to be duplicated between the VLIW register and the CGA register in response to execution of each of the VLIW logic and the CGA logic, when the processor is operated in a single execution mode, andschedule the processed data to be duplicated between the VLIW register and the CGA register after synchronizing of a termination point in time between the VLIW logic and the CGA logic, when the processor is operated in a parallel mode. 15. The method of claim 14, wherein the scheduling comprises scheduling the VLIW logic and the CGA logic to be processed in parallel based on the stored status value. 16. The method of claim 15, wherein the scheduling comprises scheduling the VLIW logic and the CGA logic to be sequentially processed based on the stored status value. 17. The method of claim 15, further comprising: storing, by a control register, pending information used to adjust a point in time for initiating a subsequent program by verifying whether an operation according to the CGA logic is terminated. 18. The method of claim 17, wherein the scheduling comprises verifying whether the operation according to the CGA logic is terminated, and duplicating a file stored in the VLIW register and moving the duplicated file to the CGA register when the operation according to the CGA logic is terminated. 19. A non-transitory computer-readable medium comprising a program for instructing a computer to perform the method of claim 14. 20. A reconfigurable processor, comprising: a status register configured to store a status value;a scheduler configured to schedule the reconfigurable processor to execute in at least one of a general mode and a special mode based on the stored status value;a general register configured to store data processed according to the general mode; anda special register configured to store data processed according to the special mode,wherein the scheduler is configured to: schedule the processed data to be duplicated between the general register and the special register in response to execution of each of the general mode and the special mode, when the general mode and the special mode are sequentially processed, andschedule the processed data to be duplicated between the general register and the special register after synchronizing of a termination point in time between the general mode and the special mode, when the general mode and the special mode are processed in parallel. 21. The reconfigurable processor of claim 20, wherein the scheduler is configured to schedule the general mode and the special mode to be processed in parallel based on the stored status value. 22. The reconfigurable processor of claim 21, wherein the scheduler is configured to schedule the generalized mode and the special mode to be sequentially processed based on the stored status value. 23. The reconfigurable processor of claim 21, further comprising: a control register configured to store pending information used to adjust when to initiate a subsequent program by verifying whether an operation according to the special mode is terminated. 24. The reconfigurable processor of claim 23, wherein the scheduler is configured to copy a file stored in the general register to the special register when the operation according to the special mode is terminated. 25. The reconfigurable processor of claim 24, wherein when the file stored in the general register is copied to the special register, the scheduler is configured to inform that the special mode is being executed by setting a value stored in the control register. 26. The reconfigurable processor of claim 25, wherein the scheduler is configured to simultaneously execute the general mode and the special mode after setting the value stored in the control register.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (4)
Gallup Michael G. (Austin TX) Goke L. Rodney (Austin TX) Seaton ; Jr. Robert W. (Austin TX), Data processing system and method thereof.
Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
Cofler,Andrew; Fel,Bruno; Ducousso,Laurent, Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.