Non-volatile memory with overwrite capability and low write amplification
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G11C-007/00
G11C-013/00
출원번호
US-0952467
(2013-07-26)
등록번호
US-9576616
(2017-02-21)
발명자
/ 주소
Nazarian, Hagop
Nguyen, Sang
출원인 / 주소
CROSSBAR, INC.
대리인 / 주소
Amin, Turocy & Watson, LLP
인용정보
피인용 횟수 :
0인용 특허 :
192
초록▼
Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory ce
Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations.
대표청구항▼
1. A solid state non-volatile memory storage drive configured to be communicatively connected to a computing device, comprising: an array of two-terminal memory elements arranged to be operable in conjunction with a plurality of wordlines and a plurality of bitlines; anda memory controller configure
1. A solid state non-volatile memory storage drive configured to be communicatively connected to a computing device, comprising: an array of two-terminal memory elements arranged to be operable in conjunction with a plurality of wordlines and a plurality of bitlines; anda memory controller configured to access at least a subset of the two-terminal memory elements, the subset comprising equal or less than a page of two-terminal memory elements, and configured to write a set of data to and overwrite the set of data at the subset of the two-terminal memory elements, wherein the memory controller is configured to overwrite the set of data without erasing a physical address location storing the set of data, providing write amplification equal to 1 for the solid state non-volatile memory storage drive. 2. The solid state non-volatile memory storage drive of claim 1, wherein the computing device comprises a memory storage device and a host controller controlling the memory storage device. 3. The solid state non-volatile memory drive of claim 2, further comprising a local wordline connected to respective two-terminal memory elements of the subset of the two-terminal memory elements at respective first terminals thereof, the local wordline configured to be activated by a wordline of the plurality of wordlines, wherein the wordline of the plurality of wordlines is configured to activate a plurality of local wordlines, including the local wordline, that are respectively connected to subsets of the two-terminal memory elements of the page of two-terminal memory elements. 4. The solid state non-volatile memory drive of claim 3, wherein activation of at least one local wordline of the plurality of local wordlines facilitates writing the set of data to and overwriting the set of data at the subset of the two-terminal memory elements connected to the at least one local wordline. 5. The solid state non-volatile memory storage drive of claim 1, wherein the subset comprises 8 or fewer two-terminal memory elements. 6. The solid state non-volatile memory storage drive of claim 1, wherein the subset comprises a single two-terminal memory element. 7. The solid state non-volatile memory storage drive of claim 1, further comprising: a set of input-output interfaces;a set of local wordlines at least in part controlled by a wordline of the plurality of wordlines; anda multiplex component configured to selectively interface respective two-terminal memory elements of a group of two-terminal memory elements with respective input-output interfaces of the set of input-output interfaces in conjunction with a memory operation. 8. The solid state non-volatile memory storage drive of claim 7, wherein the group of two-terminal memory elements includes at least two of the two-terminal memory elements that are connected to separate local wordlines of the set of local wordlines. 9. The solid state non-volatile memory storage drive of claim 8, wherein the multiplex component connects a first two-terminal memory element of the group connected to a first local wordline of the set of local wordlines to a first input-output interface of the set of input-output interfaces in conjunction with the memory operation, and connects a second two-terminal memory element of the group connected to a second local wordline of the set of local wordlines to a second input-output interface of the set of input-output interfaces. 10. The solid state non-volatile memory storage drive of claim 7, wherein: the memory controller is configured to select the respective two-terminal memory elements of the group of two-terminal memory elements from one two-terminal memory element on each respective local wordline of a subset of the set of local wordlines; andthe multiplex component facilitates interconnection of the one two-terminal memory element on each respective local wordline of the subset of the set of local wordlines of the group of two-terminal memory elements. 11. The solid state non-volatile memory storage drive of claim 7, wherein the multiplex component facilitates interconnection of one of the group of two-terminal memory elements with one of the set of input-output interfaces concurrently with disconnecting or inhibiting remaining two-terminal memory elements of the group from the set of input-output interfaces. 12. The solid state non-volatile memory storage drive of claim 11, wherein the memory controller is further configured to write to or overwrite the one of the group of two-terminal memory elements without writing to, or overwriting, the remaining two-terminal memory elements of the group. 13. A solid state non-volatile memory storage drive configured to be communicatively connected to a computing device, comprising: an array of two-terminal memory elements arranged to be operable in conjunction with a plurality of wordlines and a plurality of bitlines;a set of input-output interfaces;a set of local wordlines at least in part controlled by one of the plurality of wordlines; anda multiplex component configured to selectively interface respective two-terminal memory elements of a group of two-terminal memory elements with respective input-output interfaces of the set of input-output interfaces in conjunction with a memory operation, wherein the group of two-terminal memory elements includes at least two of the two-terminal memory elements that are connected to separate local wordlines of a plurality of local wordlines, wherein the multiplex component is further configured to connect a first two-terminal memory element of the group connected to a first local wordline of the plurality of local wordlines to a first input-output interface of the set of input-output interfaces in conjunction with the memory operation, and connect a second two-terminal memory element of the group connected to a second local wordline of the plurality of local wordlines to a second input-output interface of the set of input-output interfaces; anda memory controller configured to access at least a subset of the two-terminal memory elements, the subset comprising equal or less than a page of two-terminal memory elements, and configured to write a set of data to and overwrite the set of data at the subset of the two-terminal memory elements, providing a write amplification less than 2 and equal to or greater than one. 14. The solid state non-volatile memory storage drive of claim 13, wherein the computing device comprises a memory storage device and a host controller controlling the memory storage device. 15. The solid state non-volatile memory drive of claim 14, further comprising a local wordline connected to respective two-terminal memory elements of the subset of the two-terminal memory elements at respective first terminals thereof, the local wordline configured to be activated by one of the plurality of wordlines, wherein the one of the plurality of wordlines is configured to activate a plurality of local wordlines, including the local wordline, that are respectively connected to respective subsets of the page of two-terminal memory elements. 16. The solid state non-volatile memory drive of claim 15, wherein activation of at least one local wordline of the plurality of local wordlines facilitates writing the set of data to and overwriting the set of data at the respective subsets of two-terminal memory elements connected to the at least one local wordline. 17. The solid state non-volatile memory storage drive of claim 13, wherein the memory controller is configured to overwrite the set of data without erasing a physical address location storing the set of data, providing write amplification equal to 1 for the solid state non-volatile memory drive. 18. The solid state non-volatile memory storage drive of claim 13, wherein the subset comprises 8 or fewer two-terminal memory elements. 19. The solid state non-volatile memory storage drive of claim 13, wherein the subset comprises a single two-terminal memory element. 20. The solid state non-volatile memory storage drive of claim 13, wherein: the memory controller is configured to select the respective two-terminal memory elements of the group of two-terminal memory elements from one two-terminal memory element on each respective local wordline of a subset of the set of local wordlines; andthe multiplex component facilitates interconnection of the one two-terminal memory element on each respective local wordline of the subset of the set of local wordlines of the group of two-terminal memory elements. 21. The solid state non-volatile memory storage drive of claim 13, wherein the multiplex component facilitates interconnection of one two-terminal memory element of the group of two-terminal memory elements with one input-output interface of the set of input-output interfaces concurrently with disconnecting or inhibiting remaining two-terminal memory elements of the group from the set of input-output interfaces. 22. The solid state non-volatile memory storage drive of claim 21, wherein the memory controller is further configured to write to or overwrite the one two-terminal memory element of the group of two-terminal memory elements without writing to, or overwriting, the remaining two-terminal memory elements of the group.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (192)
Bandyopadhyay, Abhijit; Hou, Kun; Maxwell, Steven, 3D polysilicon diode with low contact resistance and method for forming same.
Owen Alan E. (Edinburgh GB6) Snell Anthony J. (Penicuik GB6) Hajto Janos (Edinburgh GB6) Lecomber Peter G. (Dundee GB6) Rose Mervyn J. (Forfar GB6), Amorphous silicon memory.
Kuramoto Yuuji,JPX ; Maekawa Hirotoshi,JPX ; Anzai Kiyoharu,JPX, Analog signal detecting circuit, and AC side current detector of semiconductor power conversion device.
Mei Ping ; Lu Jeng Ping ; Lemmi Francesco ; Street Robert A. ; Boyce James B., Continuous amorphous silicon layer sensors using doped poly-silicon back contact.
Endo Masayuki (Osaka JPX) Kawaguchi Akemi (Osaka JPX) Nishio Mikio (Osaka JPX) Hashimoto Shin (Osaka JPX), Electroless plating bath used for forming a wiring of a semiconductor device, and method of forming a wiring of a semico.
Ovshinsky Stanford R. (2700 Squirrel Rd. Bloomfield Hills MI 48013) Hudgens Stephen J. (2 Alexandria Towne Southfield MI 48075) Strand David A. (2091 Daintree West Bloomfield MI 48323) Czubatyj Wolod, Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memo.
Freeman Richard D. (San Carlos CA) Linoff Joseph D. (San Jose CA) Saxe Timothy (Los Altos CA), Logic cell and routing architecture in a field programmable gate array.
Sugiyama, Hideyuki; Saito, Yoshiaki, Magneto-resistance effect element with a surface contacting with a side face of electrode having a magnetization direction.
Schricker, April; Herner, Brad; Konevecki, Michael W., Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same.
Schricker, April; Herner, Brad; Clark, Mark, Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same.
Chen, Yung-Tin; Pan, Chuanbin; Mihnea, Andrei; Maxwell, Steven; Hou, Kun, Memory cells having storage elements that share material layers with steering elements and methods of forming the same.
Bertin, Claude L.; Huang, X. M. Henry; Rueckes, Thomas; Sivarajan, Ramesh, Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks.
Forouhi Abdul R. (San Jose CA) Hawley Frank W. (Campbell CA) McCollum John L. (Saratoga CA) Yen Yeouchung (San Jose CA), Metal-to-metal antifuse with conductive.
Luo, Xiao; Yu, David Chang-Cheng, Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory.
Ohtake, Fumio; Akasaka, Yasushi; Murakoshi, Atsushi; Suguro, Kyoichi, Method for fabricating semiconductor device having gate electrode with polymetal structure of polycrystalline silicon film and metal film.
Liaw, Corvin; Angerbauer, Michael; Hoenigschmid, Heinz, Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell.
Pruijmboom Armand ; Jansen Alexander C. L.,NLX ; Koster Ronald,NLX ; Van Der Wel Willem,NLX, Method of manufacturing a semiconductor device with a BiCMOS circuit.
Kumar, Nitin; Tong, Jinhong; Lang, Chi I; Chiang, Tony; Phatak, Prashant B., Methods for forming nonvolatile memory elements with resistive-switching metal oxides.
Eun, Sung Ho; Oh, Jae Hee; Park, Jae Hyun; Kim, Jung In; Ko, Seung Pil; Oh, Yong Tae, Methods of fabricating a semiconductor device including a self-aligned cell diode.
Lee, Thomas H.; Subramanian, Vivek; Cleeves, James M.; Walker, Andrew J.; Petti, Christopher J.; Kouznetzov, Igor G.; Johnson, Mark G.; Farmwald, Paul Michael; Herner, Brad, Monolithic three dimensional array of charge storage devices containing a planarized surface.
Hong, Edward; Ramachandran, Avinash, Motion refinement engine for use in video encoding in accordance with a plurality of sub-pixel resolutions and methods for use therewith.
Chen, Xiying; Yen, Bing K.; Nguyen, Dat; Xu, Huiwen; Samachisa, George; Kumar, Tanmay; Ping, Er-Xuan, Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same.
Manning, H. Montgomery; Rueckes, Thomas; Bertin, Claude L.; Ward, Jonathan W.; Derderian, Garo, NRAM arrays with nanotube blocks, nanotube traces, and nanotube planes and methods of making same.
Owen Alan E. (Edinburgh GB6) Sarrabayrouse Gerard (Tolouse FRX) LeComber Peter G. (Dundee GB6) Spear Walter E. (Dundee GB6), Non-volatile amorphous semiconductor memory device utilizing a forming voltage.
Takahashi, Haruo; Hanzawa, Kouichi; Matsumoto, Takafumi, Optical film thickness controlling method, optical film thickness controlling apparatus, dielectric multilayer film manufacturing apparatus, and dielectric multilayer film manufactured using the same controlling apparatus or manufacturing apparatus.
Lee, Chang-bum; Park, Young-soo; Lee, Myung-jae; Wenxu, Xianyu; Kang, Bo-soo; Ahn, Seung-eon; Kim, Ki-hwan, Resistive memory devices and methods of manufacturing the same.
Rose Mervyn J. (Angus GBX) Hajto Janos (Edinburgh GBX) Owen Alan E. (Edinburgh GBX) Osborne Ian S. (Dundee GBX) Snell Anthony J. (Midlothian GBX) Le Comber ; deceased Peter G. (late of Dundee GBX by , Resistive memory element.
Kim, Myoung Sub; Kim, Soo Gil; Park, Nam Kyun; Kim, Sung Cheoul; Do, Gap Sok; Sim, Joon Seop; Lee, Hyun Jeong, Semiconductor integrated circuit device, method of manufacturing the same, and method of driving the same.
Kim, Myoung Sub; Kim, Soo Gil; Park, Nam Kyun; Kim, Sung Cheoul; Do, Gap Sok; Sim, Joon Seop; Lee, Hyun Jeong, Semiconductor intergrated circuit device, method of manufacturing the same, and method of driving the same.
Eichman Eric C. (Phoenix AZ) Salt Thomas C. (Chandler AZ), Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method ther.
Eichman Eric C. ; Salt Thomas C., Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method ther.
Chang Shou-Zen,TWX ; Tsai Chaochieh,TWX ; Ho Chin-Hsiung ; Lin Cheng Kun,TWX, Silicon and arsenic double implanted pre-amorphization process for salicide technology.
Maddox ; III Roy L. (Boise ID) Mathews Viju K. (Boise ID) Fazan Pierre C. (Boise ID), Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of.
Gee, Harry Yue; Clark, Mark Harold; Maxwell, Steven Patrick; Jo, Sung Hyun; Vasquez, Jr., Natividad, Sub-oxide interface layer for two-terminal memory.
Sugita,Yasunari; Odagawa,Akihiro; Adachi,Hideaki; Yotsuhashi,Satoshi; Kanno,Tsutomu; Ohnaka,Kiyoshi, Variable resistance element, method of manufacturing the element, memory containing the element, and method of driving the memory.
Canaperi,Donald F.; Dalton,Timothy J.; Gates,Stephen M.; Krishnan,Mahadevaiyer; Nitta,Satya V.; Purushothaman,Sampath; Smith,Sean P. E., Very low effective dielectric constant interconnect Structures and methods for fabricating the same.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.