Content addressable memory in integrated circuit
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-017/30
G11C-015/00
G11C-015/04
출원번호
US-0356371
(2012-11-09)
등록번호
US-9583190
(2017-02-28)
국제출원번호
PCT/US2012/064546
(2012-11-09)
국제공개번호
WO2013/071183
(2013-05-16)
발명자
/ 주소
Miller, Marc
Reaves, Jimmy Lee
출원인 / 주소
Altera Corporation
인용정보
피인용 횟수 :
0인용 특허 :
63
초록▼
An integrated circuit (IC) that includes content addressable memories (CAM) is described. A CAM receives a key and searches through entries stored in the CAM for one or more entries that match the key. If a matching entry is found, the IC returns a storage address indicating a memory location at whi
An integrated circuit (IC) that includes content addressable memories (CAM) is described. A CAM receives a key and searches through entries stored in the CAM for one or more entries that match the key. If a matching entry is found, the IC returns a storage address indicating a memory location at which the matching was found.
대표청구항▼
1. An integrated circuit (IC) comprising: a first set of configurable circuits implementing a user design that performs operations by searching memories for content that matches a key;a content addressable memory (CAM); anda second set of configurable circuits implementing interface circuitry betwee
1. An integrated circuit (IC) comprising: a first set of configurable circuits implementing a user design that performs operations by searching memories for content that matches a key;a content addressable memory (CAM); anda second set of configurable circuits implementing interface circuitry between the user design and the CAM, wherein the CAM comprises: a plurality of banks, each bank comprising an array of memory cells and a set of comparison circuits for comparing content of the bank's array of memory cells with the key; anda read port for selectively retrieving content from one of the plurality of banks in the CAM and delivering the retrieved content to the user design. 2. The IC of claim 1, wherein different sets of comparison circuits in different banks of the CAM compare the content of memory cells in the different banks with the key simultaneously. 3. The IC of claim 1, wherein the key comprises a set of value bits and a set of mask bits, wherein each of the mask bits indicates whether a corresponding value bit is to be ignored when the key is being compared with the content in the CAM. 4. The IC of claim 1, wherein the array of memory cells of each bank comprises first and second sets of memory cells, wherein the first set of memory cells provides data bits for bitwise comparison with the key and the second set of memory cells provides mask bits for bitwise masking of the comparison result. 5. The IC of claim 1, wherein each bank further comprising a content retrieval circuit for selecting one word of the array of memory cells and for retrieving content from the selected word. 6. The IC of claim 5, wherein comparing the content of the bank's array of memory cells with the key comprises comparing the retrieved content from the selected word with the key. 7. The IC of claim 6, wherein the content retrieval circuit selects the word based on a selection pointer that is incremented every clock cycle. 8. The IC of claim 7, wherein the selection pointer is used by content retrieval circuits in all banks of the CAM. 9. The IC of claim 1, wherein results of the comparison from each of the plurality of banks are stored in a storage circuit that can be access by the user design. 10. The IC of claim 1, wherein results of the comparison from each of the plurality of banks are processed by a comparison result reduction circuit to find content in the CAM that matches the key. 11. An integrated circuit (IC) comprising: a first set of configurable circuits implementing a user design that is defined by a user clock, wherein the user design searches memories in the IC for content that matches a key; anda second set of configurable circuits implementing interface circuitry between the user design and a particular memory, the interface circuitry providing an address pointer to the particular memory for selecting one of a plurality of words stored in the particular memory for comparison with the key, wherein the address pointer increments a plurality of times within each cycle of the user clock. 12. The IC of claim 11, wherein the interface circuitry operates using a reconfiguration clock, wherein a user clock cycle comprises multiple reconfiguration clock cycles. 13. The IC of claim 12, wherein the reconfiguration clock is a sub-cycle clock of the user clock. 14. The IC of claim 12, wherein the comparison with the key produces one set of comparison results every reconfiguration clock cycle. 15. The IC of claim 14, wherein the comparison results are stored in a storage circuit that can be access by the user design. 16. The IC of claim 14, wherein the comparison results are processed by a comparison result reduction circuit to find content in the particular memory that matches the key, wherein the comparison result reduction circuit comprises pipeline stages that are driven by the reconfiguration clock. 17. The IC of claim 11, wherein the key comprises a set of value bits and a set of mask bits, wherein each of the mask bits indicates whether a corresponding value bit is to be ignored when the key is being compared with the content in the particular memory. 18. The IC of claim 11, wherein the particular memory comprises first and second sets of memory cells, wherein the first set of memory cells provides data bits for bitwise comparison with the key and the second set of memory cells provides mask bits for bitwise masking of the comparison result. 19. The IC of claim 11, wherein first and second sets of configurable circuits are reconfigurable circuits that reconfigure on every reconfiguration clock cycle. 20. The IC of claim 19, wherein the address pointer increments every reconfiguration clock cycle while the first set of configurable circuits is searching the particular memory for content that matches the key. 21. An integrated circuit (IC) comprising: a plurality of configurable logic circuits configured to perform a particular operation;a user defined memory comprising a plurality of configurable memory modules storing content that are accessible by the plurality of configurable logic circuits, wherein the user defined memory operates as (i) a random access memory (RAM) when the plurality of configurable memory modules is configured by a first set of configuration data, (ii) a content addressable memory (CAM) when the plurality of configurable memory modules is configured by a second set of configuration data, and (iii) a ternary content addressable memory (TCAM) when the plurality of configurable memory modules is configured by a third set of configuration data. 22. The IC of claim 21, wherein each configurable memory module comprises a set of comparison circuits for comparing a key with content stored in the configurable memory. 23. The IC of claim 22, wherein the key comprises a set of value bits and a set of mask bits, wherein each of the mask bits indicates whether a corresponding value bit is to be ignored. 24. The IC of claim 22, wherein each configurable memory comprises first and second sets of memory cells, wherein the first set of memory cells provides data bits for bitwise comparison with the key and the second set of memory cells provides mask bits for bitwise masking of the comparison result when the user defined memory is operating as a TCAM. 25. The IC of claim 24, wherein the first set of memory cells and the second set of memory cells both provide data bits for bitwise comparison with the key when the user defined memory is operating as a CAM. 26. The IC of claim 22, wherein results of said comparison from each of the plurality of configurable memory modules are stored in a storage circuit that can be access by the plurality of configurable logic circuits. 27. The IC of claim 22, wherein results of said comparison from each of the plurality of configurable memory modules are processed by a comparison result reduction circuit to find content in the user defined memory that matches the key. 28. The IC of claim 21, wherein all configurable memory modules in the user defined memory share an address pointer for selecting and retrieving content from memory cells in the configurable memory modules. 29. The IC of claim 21, wherein the user defined memory is a first user defined memory and the plurality of configurable memory modules is a first plurality of configurable memory modules, the IC further comprising a second user defined memory comprising a second plurality of configurable memory modules. 30. The IC of claim 29, wherein the second user defined memory includes fewer configurable memory modules than the first user defined memory. 31. The IC of claim 29, wherein the second user defined memory includes more configurable memory modules than the first user defined memory. 32. The IC of claim 29, wherein the second user defined memory receives a different key from the first user defined memory.
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