[미국특허]
Semiconductor package and method of manufacturing the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/02
H01L-025/065
H01L-023/00
H01L-023/498
H01L-025/00
출원번호
US-0725268
(2015-05-29)
등록번호
US-9601466
(2017-03-21)
우선권정보
KR-10-2014-0117797 (2014-09-04)
발명자
/ 주소
Yoon, Jeongwon
Noh, Boin
Lee, Baikwoo
Chun, Hyunsuk
출원인 / 주소
Samsung Electronics Co., Ltd.
대리인 / 주소
Onello & Mello, LLP.
인용정보
피인용 횟수 :
0인용 특허 :
12
초록▼
Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second p
Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.
대표청구항▼
1. A semiconductor package comprising: a first package substrate;a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the fir
1. A semiconductor package comprising: a first package substrate;a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top;a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and a second package substrate provided on the top of the first semiconductor chip, wherein the clad metal comprises at least a first layer of metal and a second layer of metal, the first layer of metal with which the clad metal is in contact with the first pad being formed of a same type of metal as the first pad; anda solder ball provided between the second layer of metal and a second pad of the one of the second semiconductor chip and the second package substrate connected thereto. 2. The semiconductor package of claim 1, wherein a recess is formed in the second layer of metal being in contact with the solder ball. 3. The semiconductor package of claim 1, wherein the clad metal and the first semiconductor chip are connected by ultrasonic bonding. 4. The semiconductor package of claim 1, wherein the clad metal and the one of the second semiconductor chip and the second package substrate is connected by ultrasonic bonding or adhesive bonding. 5. The semiconductor package of claim 1, wherein the second layer of metal at which the clad metal is in contact with the second pad is formed of a same type of metal as the second pad. 6. The semiconductor package of claim 1, wherein the first layer of metal and the second layer of metal are homogeneous or heterogeneous. 7. The semiconductor package of claim 6, wherein the first layer of metal and the second layer of metal each include one of aluminum (Al), beryllium (Be), copper (Cu), germanium (Ge), gold (Au), iron (Fe), magnesium (Mg), molybdenum (Mo), nickel (Ni), palladium (Pd), platinum (Pt), silicon (Si), silver (Ag), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), or zirconium (Zr), or a combination of two or more thereof. 8. The semiconductor package of claim 6, wherein the clad metal is formed by at least one of cladding, laminating, sputtering and plating. 9. A semiconductor package comprising: a first semiconductor chip having a first pad at a first surface thereof;a clad metal provided on the first pad and configured to electrically connect the first semiconductor device to a component, wherein the component comprises one of a second semiconductor chip and a package substrate; andwherein the clad metal comprises at least a first layer of metal and a second layer of metal, the first layer of metal with which the clad metal is in contact with the first pad being formed of a same type of metal as the first pad; anda solder ball provided between the second layer of metal and a second pad of the one of the second semiconductor chip and the package substrate connected thereto. 10. The semiconductor package of claim 9, wherein a recess is formed in the second layer of metal being in contact with the solder ball. 11. A semiconductor package comprising: a first package substrate;a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top;a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and a second package substrate provided on the top of the first semiconductor chip, the clad metal comprising at least a first layer of metal and a second layer of metal, the first layer of metal with which the clad metal is in contact with the first pad being formed of a same type of metal as the first pad; anda solder ball provided between the second layer of metal and a second pad of the one of the second semiconductor chip and the second package substrate connected thereto. 12. The semiconductor package of claim 11, wherein a recess is formed in the second layer of metal being in contact with the solder ball. 13. The semiconductor package of claim 11, wherein the second layer of metal at which the clad metal is in contact with the second pad is formed of a same type of metal as the second pad. 14. The semiconductor package of claim 11, wherein the first layer of metal and the second layer of metal are homogeneous or heterogeneous. 15. The semiconductor package of claim 14, wherein the first layer of metal and the second layer of metal each include one of aluminum (Al), beryllium (Be), copper (Cu), germanium (Ge), gold (Au), iron (Fe), magnesium (Mg), molybdenum (Mo), nickel (Ni), palladium (Pd), platinum (Pt), silicon (Si), silver (Ag), tantalum (Ta), tin (Sn), titanium (Ti), tungsten (W), or zirconium (Zr), or a combination of two or more thereof.
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