[미국특허]
Body diode conduction optimization in MOSFET synchronous rectifier
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02M-003/335
H02M-001/38
H02M-001/00
H02M-003/158
출원번호
US-0678932
(2015-04-04)
등록번호
US-9608532
(2017-03-28)
발명자
/ 주소
Wong, Pitleong
Ren, Yuancheng
Zhou, Xunwei
출원인 / 주소
JoulWatt Technology Inc. Limited
인용정보
피인용 횟수 :
2인용 특허 :
6
초록▼
To maximize power efficiency, dead time between “on” times of a synchronous rectifier (“SR”) MOSFET switch and a main switch for CCM operation in particular in isolated and non-isolated self-driven synchronous DC-DC converters needs to be optimized. To accomplish that objective, the latest conductio
To maximize power efficiency, dead time between “on” times of a synchronous rectifier (“SR”) MOSFET switch and a main switch for CCM operation in particular in isolated and non-isolated self-driven synchronous DC-DC converters needs to be optimized. To accomplish that objective, the latest conduction time t of a body diode of the SR MOSFET following conduction thereof is determined, compared with a selected fixed optimum period T1, and incrementally or decrementally adjusted in a subsequent switching cycle while t is unequal to T1, depending on whether t is shorter or longer than T1, so that t eventually is made substantially equal to T1 in length. This process is to be repeated continuously.
대표청구항▼
1. An apparatus comprising: a first input voltage terminal and a second input voltage terminal connected to ground;an output module comprising a first output voltage terminal and a second output voltage terminal, and an output-filter capacitor to be connected across said two output voltage terminals
1. An apparatus comprising: a first input voltage terminal and a second input voltage terminal connected to ground;an output module comprising a first output voltage terminal and a second output voltage terminal, and an output-filter capacitor to be connected across said two output voltage terminals;a main switch to be disposed between said two input voltage terminals;a synchronous rectifier (“SR”) MOSFET included in a non-resonant DC-DC converter having a gate control terminal and a distal end to be connectable to the output module;a switch connector to connect the main switch with the SR MOSFET, said switch connector is selected from the group consisting of a) a transformer with a primary winding and a secondary winding and b) a pair of electrical leads;an SR turn-off signal generator to provide an SR turn-off signal to terminate conduction of the SR MOSFET at an appropriate time to make conduction time t of a body diode thereof in a subsequent switching cycle substantially equal to a selected fixed optimum period T1 in each switching cycle, said signal generator comprising: a body diode conduction detector to detect a latest said conduction time t of said body diode subsequent to an end of the SR MOSFET conduction; anda body diode conduction optimizer to compare durations between said conduction time t and T1, said body diode conduction optimizer to increase an SR turn-off threshold current (“IBT”) in response to said conduction time t being shorter than T1 by outputting said SR turn-off signal sooner than the end point of said latest SR MOSFET conduction, and to decrease the IBT in response to said conduction time t being longer than T1 by outputting said SR turn-off signal later than the end point of said latest SR MOSFET conduction; anda self-synchronized control circuit having an output to be connected to said gate control terminal, said self-synchronized control circuit to turn the SR MOSFET on and off, wherein said SR MOSFET turning off occurs responsive to receiving said SR turn-off signal outputted by said body diode conduction optimizer. 2. The apparatus of claim 1, wherein if the switch connector is the transformer, the primary winding is to be connected between the first input voltage terminal and the main switch, and the secondary winding is to be connected between a proximal end of the SR MOSFET and the second output voltage terminal. 3. The apparatus of claim 1, wherein if the switch connector is the pair of electrical leads, the main switch and the SR MOSFET are to be connected in series at a switch node with the pair of electrical leads, and the second voltage output terminal is to be connected to ground. 4. The apparatus of claim 3, further comprising an inductor to be connected between said switch node and a terminal selected from the group consisting of the first output voltage terminal, the first input voltage terminal and ground. 5. The apparatus of claim 1, wherein said body diode conduction detector comprises a first voltage comparator with a non-inverting input and an inverting input to be connected to the source end and the drain end of the SR MOSFET, respectively, said first voltage comparator to have an output voltage rising from low to high responsive to the source voltage's exceeding the drain voltage, producing a first pulse with pulse width equal to said conduction time t. 6. The apparatus of claim 5, wherein said body diode conduction detector further comprises a single-pulse generator, responsive to triggering on the rising edge of the first pulse, said single-pulse generator to produce a second pulse with pulse width equal to T1, whereby the rising edges of the first pulse and the second pulse are synchronously aligned. 7. The apparatus of claim 6, wherein said body diode conduction optimizer comprises a pulse width comparison module having an output terminal, said pulse width comparison module to compare the pulse width of the first pulse with the pulse width of the second pulse to determine which of said two pulses terminates last and to provide a current for charging or a current for discharging a capacitor Cv1 to be connected between said module's output terminal and a ground with a voltage V1 thereacross. 8. The apparatus of claim 7, wherein the voltage V1 across the capacitor Cv1 is made incrementable or decrementable by such an amount as equal to a product of the amount of said charging current or the amount of said discharging current and a selected time segment divided by Cv1's capacitance, depending on whether said conduction time t is shorter or longer than T1. 9. The apparatus of claim 8, wherein said body diode conduction optimizer further comprises a feedback loop provided by a voltage V1-controlled current source I1 to be connected between said output terminal of said pulse width comparison module and a proximal end of a resistor R1. 10. The apparatus of claim 9, wherein said body diode conduction optimizer further comprises a second voltage comparator having an output to be connected to said self-synchronizing control circuit, said second voltage comparator to connect a non-inverting input thereof to a distal end of the resistor R1, thereby routing current I1 therethrough to produce a voltage drop, to connect an inverting input thereof essentially to said drain-to-source voltage of SR MOSFET, and to output a voltage rising from low to high when the former input voltage exceeds the latter input voltage, resulting in outputting said SR turn-off signal, whereby said SR turn-off signal is transmitted to said self synchronizing control circuit to terminate the conduction of SR MOSFET. 11. The apparatus of claim 8, wherein said body diode conduction optimizer further comprise a current source supplying a constant current I2, an SR MOSFET conduction interval generating (“SCIG”) MOSFET, a capacitor Cc, and a logic inverter, said current source I2 to be connected to a drain of said SCIG MOSFET, said SCIG MOSFET having a source connected to ground and a gate control terminal to be connected to an output of said logic inverter, said capacitor Cc to be connected between the drain and the source of said SCIG MOSFET, and said logic inverter to have an input connected to the gate control terminal of the SR MOSFET. 12. The apparatus of claim 11, wherein said body diode conduction optimizer further comprises a third voltage comparator with an output connected to said self-synchronized control circuit, said third voltage comparator to have a voltage across said capacitor Cc connected to a non-inverting input and the voltage V1 across the capacitor Cv1 connected to an inverting input and to have an output voltage rising from low to high when the former voltage exceeds the latter voltage, resulting in outputting said SR turnoff signal, whereby a conduction interval of the SR MOSFET is generated, which is equal to a product of Cc's capacitance and V1 divided by I2. 13. A system comprising: an alternating current (“AC”) power source;an input rectifier to convert said AC to direct current (“DC”);an input filter to smooth an output of said input rectifier;a power factor correction (“PFC”) controller connected to the input filter to shape the output current of the input filter and produce a DC output with a maximum power factor, the PFC controller to have two output terminals; anda non-resonant synchronous rectification DC-DC converter comprising: a first input voltage terminal and a second input voltage terminal connected to ground, said two input terminals to be externally connected to the two output terminals of the PFC controller;an output module comprising a first output voltage terminal and a second output voltage terminal, and an output-filter capacitor to be connected across said two output voltage terminals;a main switch to be disposed between said two input voltage terminals;a synchronous rectifier (“SR”) MOSFET having a gate control terminal and a distal end to be connectable to the output module;a switch connector to connect the main switch with the SR MOSFET, said switch connector is selected from the group consisting of a) a transformer with a primary winding and a secondary winding and b) a pair of electrical leads;an SR turn-off signal generator to provide an SR turn-off signal to terminate conduction of the SR MOSFET at an appropriate time to make conduction time t of a body diode thereof in a subsequent switching cycle substantially equal to a selected fixed optimum period T1 in each switching cycle, said signal generator comprising: a body diode conduction detector to detect a latest said conduction time t of said body diode subsequent to an end of the SR MOSFET conduction; anda body diode conduction optimizer to compare durations between said conduction time t and T1, said body diode conduction optimizer to increase an SR turn-off threshold current (“IBT”) in response to said conduction time t being shorter than T1 by outputting said SR turn-off signal sooner than the end point of said latest SR MOSFET conduction, and to decrease the IBT in response to said conduction time t being longer than T1 by outputting said SR turn-off signal later than the end point of said latest SR MOSFET conduction; anda self-synchronized control circuit having an output to be connected to said gate control terminal, said self-synchronized control circuit to turn the SR MOSFET on and off, wherein said SR MOSFET turning off occurs responsive to receiving said SR turn-off signal outputted by said body diode conduction optimizer. 14. The system of claim 13, wherein if the switch connector is the transformer, the primary winding is to be connected between the first input voltage terminal and the main switch, and the secondary winding is to be connected between a proximal end of the SR MOSFET and the second output voltage terminal. 15. The system of claim 13, wherein if the switch connector is the pair of electrical leads, the main switch and the SR MOSFET are to be connected in series at a switch node with the pair of electrical leads, and the second voltage output terminal is to be connected to ground. 16. The system of claim 15, further comprising an inductor to be connected between said switch node and a terminal selected from the group consisting of the first output voltage terminal, the first input voltage terminal and ground. 17. The system of claim 13, wherein said body diode conduction detector comprises a first voltage comparator with a non-inverting input and an inverting input to be connected to the source end and the drain end of the SR MOSFET, respectively, said first voltage comparator to have an output voltage rising from low to high responsive to the source voltage's exceeding the drain voltage, producing a first pulse with pulse width equal to said conduction time t. 18. The system of claim 17, wherein said body diode conduction detector further comprises a single-pulse generator, responsive to triggering on the rising edge of the first pulse, said single-pulse generator to produce a second pulse with pulse width equal to T1, whereby the rising edges of the first pulse and the second pulse are synchronously aligned. 19. The system of claim 18, wherein said body diode conduction optimizer comprises a pulse width comparison module having an output terminal, said pulse width comparison module to compare the pulse width of the first pulse with the pulse width of the second pulse to determine which of said two pulses terminates last and to provide a current for charging or a current for discharging a capacitor Cv1 to be connected between said module's output terminal and a ground with a voltage V1 thereacross. 20. The system of claim 19, wherein the voltage V1 across the capacitor Cv1 is made incrementable or decrementable by such an amount as equal to a product of the amount of said charging current or the amount of said discharging current and a selected time segment divided by Cv1's capacitance, depending on whether said conduction time t is shorter or longer than T1. 21. The system of claim 20, wherein said body diode conduction optimizer further comprises a feedback loop provided by a voltage V1-controlled current source I1 to be connected between said output terminal of said pulse width comparison module and a proximal end of a resistor R1. 22. The system of claim 21, wherein said body diode conduction optimizer further comprises a second voltage comparator having an output to be connected to said self-synchronizing control circuit, said second voltage comparator to connect a non-inverting input thereof to a distal end of the resistor R1, thereby routing current I1 therethrough to produce a voltage drop, to connect an inverting input thereof essentially to said drain-to-source voltage of SR MOSFET, and to output a voltage rising from low to high when the former input voltage exceeds the latter input voltage, resulting in outputting said SR turn-off signal, whereby said SR turn-off signal is transmitted to said self synchronizing control circuit to terminate the conduction of SR MOSFET. 23. A method for optimizing body diode conduction in a synchronous rectifier (“SR”) MOSFET included in a non-resonant DC-DC converter comprising: a) detecting conduction time t of a body diode of the SR MOSFET subsequent to an end of conduction thereof in a latest switching cycle;b) comparing said conduction time t with a selected fixed optimum time period T1;c) increasing an SR turn-off threshold current (“IBT”) in response to said conduction time t being shorter than T1 by terminating said SR MOSFET conduction sooner than the end point of said latest SR MOSFET conduction, and decreasing the IBT in response to said conduction time t being longer than T1 by terminating said SR MOSFET conduction later than the end point of said latest SR MOSFET conduction; andd) continuously repeating steps a-c to make said conduction time t substantially equal to T1 in length repeatedly.
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이 특허에 인용된 특허 (6)
Fu, Yi-Chiang; Chang, Wei-Hsu, Control circuit and method for a digital synchronous switching converter.
Phadke,Vijay Gangadhar; Asuncion,Arlaindo Vitug; Cabbab Caubang,Richard Daniel, Method and apparatus for reducing body diode conduction of synchronous rectifiers.
Choi, Hangseok; Chen, Lei; Chen, Cheng-Sung, Self-tuning adaptive dead time control for continuous conduction mode and discontinuous conduction mode operation of a flyback converter.
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