초록 ▼

A system and method for testing a wireless data packet signal transceiver device under test (DUT) by using DUT control circuitry separate from a tester to access and execute test program instructions for controlling the DUT during testing with the tester. The test program instructions can be provide

A system and method for testing a wireless data packet signal transceiver device under test (DUT) by using DUT control circuitry separate from a tester to access and execute test program instructions for controlling the DUT during testing with the tester. The test program instructions can be provided previously and stored for subsequent access and execution under control of the tester or an external control source, such a personal computer. Alternatively, the test program instructions can be provided by the tester or external control source immediately prior to testing, such as when beginning testing of a DUT with new or different performance characteristics or requirements. Accordingly, specialized testing of different DUTs while accounting for differences among various chipsets employed by the DUTs can be performed in coordination with a standard tester configuration without need for reconfiguring or reprogramming of the tester.

대표청구항 ▼

1. An apparatus including a system for testing data packet signal transceiver device under test (DUT), comprising: a data packet signal path for communicating with a DUT to convey a transmit data packet signal from said DUT and a receive data packet signal to said DUT;an external command source to p

1. An apparatus including a system for testing data packet signal transceiver device under test (DUT), comprising: a data packet signal path for communicating with a DUT to convey a transmit data packet signal from said DUT and a receive data packet signal to said DUT;an external command source to provide one or more test commands related to said transit data packet signal;a tester coupled to said external command source and said data packet signal path to receive said transmit data packet signal and provide said receive data packet signal, and responsive to said one or more test commands by providing one or more test control signals;a DUT control signal interface for communicating with said DUT to convey at least one DUT control signal to said DUT; andDUT control circuitry coupled between said external command source, said tester and said DUT control signal interface, and responsive to at least one of said one or more test control signals, andsaid one or more test commands,by performing at least one of executing a plurality of test program operations to provide said at least one DUT control signal,providing another DUT control signal to initiate transmission of said transmit data packet signal from said DUT,providing another DUT control signal to terminate transmission of said transmit data packet signal from said DUT, andproviding another DUT control signal to initiate reception of said receive data packet signal to said DUT;wherein said external command source provides said one or more test commands to enable testing of said DUT, following which said tester, responsive to said one or more test commands, provides said one or more test control signals, andsaid DUT control circuitry, responsive to at least one of said one or more test control signals and said one or more test commands, controls said testing of said DUT by performing at least one of said executing and providing steps. 2. The apparatus of claim 1, wherein said data packet signal path comprises a conductive radio frequency (RF) signal path. 3. The apparatus of claim 1, wherein said DUT control signal interface comprises a plurality of electrical signal conductors. 4. The apparatus of claim 1, wherein said DUT control circuitry comprises processing circuitry and memory circuitry responsive to said at least said one or more test control signals by: accessing a plurality of test program instructions from said memory circuitry; andexecuting said plurality of test program instructions with said processing circuitry. 5. The apparatus of claim 4, wherein said processing circuitry comprises microcontroller circuitry. 6. The apparatus of claim 1, wherein said DUT control circuitry comprises processing circuitry responsive to said at least said one or more test control signals by: accessing a plurality of test program instructions from said external instruction source; andexecuting said plurality of test program instructions with said processing circuitry. 7. The apparatus of claim 6, wherein said processing circuitry comprises microcontroller circuitry. 8. The apparatus of claim 1, wherein: said DUT control signal interface is further for communicating with said DUT to convey at least one test response signal from said DUT; andsaid DUT control circuitry is further responsive to said at least one test response signal by terminating said executing of said plurality of test program instructions. 9. A method of testing a data packet signal transceiver device under test (DUT), comprising: receiving, with a tester, a transmit data packet signal from a DUT;transmitting, with said tester, a receive data packet signal to said DUT;receiving, from an external command source, one or more test commands related to said transmit data packed signal;responding, with said tester, to said one or more test commands by providing one or more test control signals; andresponding, with DUT control circuitry, to at least one of said one or more test control signals andsaid one or more test commands,by performing at least one of executing a plurality of test program operations to provide at least one DUT control signal to said DUT,providing another DUT control signal to initiate transmission of said transmit data packet signal from said DUT,providing another DUT control signal to terminate transmission of said transmit data packet signal from said DUT, andproviding another DUT control signal to initiate reception of said receive data packet signal to said DUT;wherein said one or more test commands enable testing of said DUT, following which said tester, responsive to said one or more test commands, provides said one or more test control signals, andsaid DUT control circuitry, responsive to at least one of said one or more test control signals and said one or more test commands, controls said testing of said DUT by performing at least one of said executing and providing steps. 10. The method of claim 9, wherein said responding, with DUT control circuitry, to at least said one or more test control signals by executing a plurality of test program operations to provide at least one DUT control signal to said DUT comprises: accessing a plurality of test program instructions from a local instruction source; andexecuting said plurality of test program instructions. 11. The method of claim 10, wherein said executing said plurality of test program instructions comprises executing said plurality of test program instructions with microcontroller circuitry. 12. The method of claim 9, wherein said responding, with DUT control circuitry, to at least said one or more test control signals by executing a plurality of test program operations to provide at least one DUT control signal to said DUT comprises: accessing a plurality of test program instructions from said external instruction source; andexecuting said plurality of test program instructions. 13. The method of claim 12, wherein said executing said plurality of test program instructions comprises executing said plurality of test program instructions with microcontroller circuitry. 14. The method of claim 9, further comprising receiving, with said DUT control circuitry, at least one test response signal from said DUT and in response thereto terminating said executing of said plurality of test program instructions.