Packaged microelectronic elements having blind vias for heat dissipation
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/02
H01L-023/367
H01L-025/065
H01L-021/768
H01L-023/538
H01L-023/00
출원번호
US-0145288
(2013-12-31)
등록번호
US-9620433
(2017-04-11)
발명자
/ 주소
Fisch, David Edward
출원인 / 주소
Tessera, Inc.
인용정보
피인용 횟수 :
0인용 특허 :
44
초록▼
System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top su
System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind vias to other connecting components.
대표청구항▼
1. A method for fabricating a microelectronic unit, said method comprising: forming a first semiconductor element having a first top surface and a first bottom surface remote from said first top surface;forming a first semiconductor device adjacent to said first top surface, wherein said first semic
1. A method for fabricating a microelectronic unit, said method comprising: forming a first semiconductor element having a first top surface and a first bottom surface remote from said first top surface;forming a first semiconductor device adjacent to said first top surface, wherein said first semiconductor device comprises an active region of said first semiconductor element;forming a first blind via extending from said first bottom surface toward said first top surface directly below said active region of said first semiconductor device and toward said active region and partially into a thickness of said first semiconductor element;filling said first blind via with a thermally conductive material for dissipating heat generated from said first semiconductor device;forming a second semiconductor element having a second top surface and a second bottom surface remote from said second top surface;forming a second semiconductor device adjacent to said second top surface;forming a second blind via extending from said second bottom surface toward said second top surface directly below said active region of said second-semiconductor device and partially into a thickness of said second semiconductor element;filling said second blind via with said thermally conductive material for dissipating heat generated from said second semiconductor device; andstacking said second semiconductor device on said first semiconductor device. 2. The method of claim 1, further comprising: forming electrically conductive material placed in contact with said thermally conductive material of said second blind via, wherein said electrically conductive material is configured to have adjacent portions of said electrically conductive material interconnected in a mesh structure, and wherein said thermally conductive material of each of said first blind via and said second blind via is also electrically conductive. 3. The method of claim 1, further comprising: forming an insulating layer adjacent to said second bottom surface, said insulating layer having a rear surface remote from said second bottom surface;extending said second blind via through said insulating layer; andforming an electrically conductive material placed in contact with said thermally conductive material of said second blind via, wherein said electrically conductive material is configured to have adjacent portions of said electrically conductive material interconnected in a mesh structure, and wherein said thermally conductive material of each of said first blind via and said second blind via is also electrically conductive. 4. The method of claim 1, further comprising: forming a plurality of blind vias extending from said second bottom surface and partially into said thickness of said second semiconductor element;filling said plurality of blind vias with said thermally conductive material;forming a plurality of solder balls at said second bottom surface, wherein each solder ball of the plurality of solder balls is connected for thermal conductivity with said thermally conductive material of a corresponding blind via of the plurality of blind vias; andwherein said plurality of blind vias are configured to have adjacent solder balls in contact with one another to form a conductive mesh. 5. The method of claim 4, further comprising: forming a dielectric layer adjacent said second semiconductor device;forming a through via extending through said semiconductor element and said dielectric layer;filling said through via with an electrically conductive material; andconnecting said electrically conductive material with said conductive mesh. 6. A method of fabricating a microelectronic unit, said method comprising: forming a first semiconductor element having a first top surface and a first bottom surface remote from said top surface;forming a first semiconductor device adjacent to said first top surface;forming one or more first blind vias extending from said first bottom surface directly below said active region of said first semiconductor device and partially into a thickness of said first semiconductor element;filling each of said one or more first blind vias with a first thermally conductive material;forming first electrically conductive structures with electrically conductive material in contact with said first thermally conductive material, wherein said first thermally conductive material is also electrically conductive, and wherein said first electrically conductive structures are configured to have adjacent portions thereof interconnected to one another to form a mesh structure;forming a second semiconductor element having a second top surface and a second bottom surface remote from said second top surface;forming a second semiconductor device adjacent to said top surface;forming one or more second blind vias extending from said second bottom surface directly below said active region of said second semiconductor device and partially into a thickness of said second semiconductor element;filing each of said one or more second blind vias with second thermally conductive material;forming second electrically conductive structures with the electrically conductive material connected to said second thermally conductive material; andstacking said first semiconductor device and said second semiconductor device with said second semiconductor device in an opposing orientation with respect to said first semiconductor device for having said first electrically conductive structures and said second electrically conductive structures between said first semiconductor element and said second semiconductor element. 7. The method of claim 6, further comprising: forming an insulating layer adjacent to said first bottom surface, said insulating layer having a rear surface remote from said first bottom surface, wherein each of said one or more first blind vias extends from said rear surface and through said insulating layer and into said first semiconductor element. 8. The method of claim 6, wherein said first electrically conductive structures comprise a plurality of solder balls. 9. The method of claim 6, further comprising: forming a through via extending through said microelectronic unit;filling said through via with said second thermally conductive material; andconnecting said second electrically conductive structures to said second thermally conductive material. 10. The method of claim 6, further comprising: forming a dielectric element adjacent to said second semiconductor device, said dielectric element having a front surface remote from said second semiconductor device. 11. The method of claim 6, further comprising: forming a package including said first semiconductor device and said second semiconductor device, wherein said mesh structure is electrically coupled to one or more terminals leading externally to said package. 12. The method of claim 6, further comprising: forming a barrier metal lining in at least one of said one or more first blind vias and separating said first thermally conductive material from said first semiconductor element. 13. The method of claim 6, wherein said first semiconductor device comprises a DRAM array.
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