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A charge pump circuit is coupled between a positive supply node and a ground node. The charge pump circuit operates in response to clock signals output from a clock generator to produce a negative voltage at a negative voltage output node. A soft-start circuit for the charge pump circuit includes a

A charge pump circuit is coupled between a positive supply node and a ground node. The charge pump circuit operates in response to clock signals output from a clock generator to produce a negative voltage at a negative voltage output node. A soft-start circuit for the charge pump circuit includes a comparison circuit configured to compare a varying intermediate voltage sensed between a rising supply voltage and the negative voltage to a ramp voltage during a start-up period of the charge pump circuit. The clock generator is selectively enabled to generate the clock signals in response to the comparison to provide for pulse-skipping.

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1. A circuit, comprising: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit operating in response to a plurality of clock signals output from a clock generator to produce a negative voltage at a negative voltage output node, said charge pump cir

1. A circuit, comprising: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit operating in response to a plurality of clock signals output from a clock generator to produce a negative voltage at a negative voltage output node, said charge pump circuit comprising: a first transistor having a source-drain path coupled between the positive supply node and an intermediate node and controlled by a first signal of said plurality of clock signals;a second transistor having a source-drain path coupled between the intermediate node and the ground node; anda third transistor having a source-drain path coupled between the intermediate node and the ground node and controlled by a second signal of said plurality of clock signals; anda soft-start circuit for said charge pump circuit comprising: a comparison circuit configured to compare an intermediate voltage between a supply voltage and the negative voltage to a falling ramp voltage during a start-up of the charge pump circuit and selectively apply said second signal of said plurality of clock signals in response to said comparison to control said second transistor. 2. The circuit of claim 1, wherein said comparison circuit comprises a comparator having a first input coupled to receive the intermediate voltage and a second input coupled to receive the falling ramp voltage, said comparator further having an output generating a soft-start complete signal, wherein the second signal of said plurality of clock signals is applied to control the second transistor in response to said soft-start complete enable signal. 3. The circuit of claim 1, wherein said soft-start circuit further comprises a resistive divider circuit coupled between a supply node for the rising supply voltage and the negative voltage output node, said resistive divider circuit having a tap node generating the intermediate voltage. 4. A circuit, comprising: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit operating in response to a plurality of clock signals output from a clock generator to produce a negative voltage at a negative voltage output node;a soft-start circuit for said charge pump circuit comprising: a comparison circuit configured to compare an intermediate voltage between a supply voltage and the negative voltage to a falling ramp voltage during a start-up of the charge pump circuit and selectively enable the clock generator to generate said plurality of clock signals in response to said comparison;a resistive divider circuit coupled between a supply node for the rising supply voltage and the negative voltage output node, said resistive divider circuit having a first tap node generating the intermediate voltage and a second tap node generating an additional intermediate voltage less than said intermediate voltage; andan additional comparison circuit configured to compare the additional intermediate voltage to the falling ramp voltage during the start-up of the charge pump circuit and selectively enable a drive transistor within the charge pump circuit in response to said additional comparison. 5. The circuit of claim 4, wherein said charge pump circuit further comprises an additional transistor coupled in parallel with said drive transistor, said additional transistor driven by one of said plurality of clock signals and said drive transistor driven by the one of said plurality of clock signals only when selectively enabled by the additional comparison circuit. 6. The circuit of claim 5, wherein said additional transistor is smaller than said drive transistor. 7. A circuit, comprising: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit including a clock generator configured to generate a plurality of clock signals, the charge pump circuit responding to said plurality of clock signals to produce a negative voltage at a negative voltage output node; anda soft-start circuit for said charge pump circuit operating to cause pulse skipping of the plurality of clock signals during soft-start, said pulse skipping occurring each time an intermediate voltage that is sensed by the soft-start circuit between a supply voltage and the negative voltage crosses over a ramp voltage;wherein said charge pump circuit comprises: a first drive transistor having a first control terminal configured to receive one of the plurality of clock signals;a second drive transistor connected in parallel with the first drive transistor and having a second control terminal;wherein said soft-start circuit comprises a logic gate configured to block application of said one of the plurality of clock signals to the second control terminal for a duration of a soft-start period and then pass said one of the plurality of clock signals to the second control terminal after the soft-start period ends. 8. The circuit of claim 7, wherein the soft-start circuit comprises a comparison circuit configured to compare said intermediate voltage to the ramp voltage and generate an enable signal, said clock generator operating in response to said enable signal. 9. The circuit of claim 7, wherein said soft-start circuit further comprises a resistive divider circuit coupled between a supply node for the supply voltage and the negative voltage output node, said resistive divider circuit having a tap node generating the intermediate voltage. 10. The circuit of claim 7, wherein said soft-start circuit further comprises: a resistive divider circuit coupled between a supply node for the supply voltage and the negative voltage output node, said resistive divider circuit having a first tap node generating a threshold voltage; anda comparator circuit configured to compare the ramp voltage to the threshold voltage to generate an end of soft-start period signal for application to said logic gate. 11. The circuit of claim 10, wherein said resistive divider circuit further has a second tap node generating said intermediate voltage. 12. The circuit of claim 7, wherein said first drive transistor is smaller than said second drive transistor. 13. A circuit, comprising: a charge pump circuit having a negative voltage output node and including: a first CMOS switching circuit coupled between a positive supply node and a ground node and configured to receive first and second clock signals and having a first output;a second CMOS switching circuit coupled between the ground node and the negative voltage output node and configured to receive third and fourth clock signals and having a second output;wherein the first and second outputs are configured for connecting to opposite plates of a fly capacitor; anda clock generator circuit configured to generate the first through fourth clock signals; anda soft-start circuit for said charge pump circuit, the soft-start circuit comprising: a resistive voltage divider having at least a first tap node and a second tap node, the resistive voltage divider coupled between a supply voltage node and the negative voltage output node;a ramp signal generator configured to generate a ramp signal;a first comparator configured to compare a voltage at the first tap node to a voltage of the ramp signal to generate a first enable signal applied to control enabling of the clock generator circuit to generate the first through fourth clock signals; anda second comparator configured to compare a voltage at the second tap node to the voltage of the ramp signal to generate a second enable signal applied to control enabling of a transistor within the first CMOS switching circuit. 14. The circuit of claim 13, wherein the first CMOS switching circuit comprises: a p-channel MOSFET; andan n-channel MOSFET;wherein the p-channel and n-channel MOSFETs are connected in series; andwherein the second enable signal is configured to enable operation of the n-channel MOSFET. 15. The circuit of claim 14, wherein the soft-start circuit further comprises: an additional MOSFET coupled in parallel with the n-channel MOSFET, said additional MOSFET having a control terminal configured to receive one of the first through fourth clock signals; andwherein the n-channel MOSFET has a control terminal that is selectively enabled by the second enable signal to receive said one of the first through fourth clock signals. 16. The circuit of claim 15, wherein the soft-start circuit further comprises a logic gate having a first input configured to receive said one of the first through fourth clock signals, a second input configured to receive the second enable signal, and an output coupled to the control terminal of the n-channel MOSFET. 17. The circuit of claim 16, wherein the logic gate is an AND gate. 18. The circuit of claim 15, wherein said additional MOSFET is smaller than said n-channel MOSFET. 19. A circuit, comprising: a charge pump circuit coupled between a positive supply node and a ground node, said charge pump circuit including a clock generator configured to generate a plurality of clock signals, the charge pump circuit responding to said plurality of clock signals to produce a negative voltage at a negative voltage output node;wherein said charge pump circuit comprises: a first drive transistor having a first control terminal configured to receive one of the plurality of clock signals;a second drive transistor connected in parallel with the first drive transistor and having a second control terminal; anda soft-start circuit for said charge pump circuit comprising a logic gate configured to block application of said one of the plurality of clock signals to the second control terminal for a duration of a soft-start period and then pass said one of the plurality of clock signals to the second control terminal after the soft-start period ends;said soft-start circuit further comprising: a resistive divider circuit coupled between a supply node for the supply voltage and the negative voltage output node, said resistive divider circuit having a tap node generating a threshold voltage; anda comparator circuit configured to compare a ramp voltage to the threshold voltage to generate an end of soft-start period signal for application to said logic gate. 20. The circuit of claim 19, wherein said first drive transistor is smaller than said second drive transistor.