Simultaneous formation of liner and metal conductor
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/02
H01L-023/528
H01L-023/532
H01L-021/768
H01L-021/8234
H01L-023/52
출원번호
US-0217566
(2016-07-22)
등록번호
US-9721788
(2017-08-01)
발명자
/ 주소
Edelstein, Daniel C
Yang, Chih-Chao
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
LaBaw, Jeffrey S
인용정보
피인용 횟수 :
0인용 특허 :
9
초록▼
In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes providing a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls
In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes providing a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element. A wetting layer is deposited on the first metal layer. A second thermal anneal is preformed which reflows the wetting layer to fill a second portion of the conductive line trenches. A second metal layer is deposited on the wetting layer. A second thermal anneal is performed which reflows the second metal layer to fill a remaining portion of the conductive line trenches. Another aspect of the invention is a device formed by the method.
대표청구항▼
1. A method for fabricating an advanced metal conductor structure comprising: providing a conductive line pattern including a set of conductive line trenches in a dielectric layer, each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom;p
1. A method for fabricating an advanced metal conductor structure comprising: providing a conductive line pattern including a set of conductive line trenches in a dielectric layer, each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom;performing a surface treatment of the dielectric layer, the surface treatment producing an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased;depositing a first metal layer on the element enriched surface layer;performing a first thermal anneal which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element;depositing a wetting layer on the first metal layer;performing a second thermal anneal which reflows the wetting layer to fill a second portion of the conductive line trenches;depositing a second metal layer on the wetting layer; andperforming a third thermal anneal which reflows the second metal layer to fill a remaining portion of the conductive line trenches. 2. The method as recited in claim 1 wherein the first metal layer is comprised of aluminum and the selected element is nitrogen. 3. The method as recited in claim 2, wherein the surface treatment is a nitridation process which increases the concentration of nitrogen in the element enriched surface layer and the liner is comprised of an alloy selected from the group consisting of AlN and Al(N, Si) and Al(N, Si, Mn). 4. The method as recited in claim 1, wherein the first metal layer is comprised of a metal selected from the group consisting of Al, Co, Ru, Ir, Rh, W and Ni and the second metal layer is a metal selected from the group of Cu, Co, W, Ir, Rh, Ni and Ru. 5. The method as recited in claim 1, wherein the selected element is selected from the group consisting of N, Si, C, and O. 6. The method as recited in claim 1, further comprising removing excess first and second metal layers on field areas of the dielectric layer using a planarization process. 7. The method as recited in claim 1, wherein the wetting layer is selected from the group of Co, Ru, Ir and Rh. 8. The method as recited in claim 1, wherein the second metal layer is selected from the group of CuMn, CoMn, WMn, IrMn, RhMn, NiMn and RuMn and wherein the second thermal anneal drives manganese into the liner. 9. The method as recited in claim 1, further comprising depositing a barrier layer over the first metal layer before the second metal layer. 10. The method as recited in claim 1, wherein the total aspect ratio of the conductive lines is greater than 2.5.
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이 특허에 인용된 특허 (9)
Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
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