Semiconductor device and method of manufacturing the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/11
H01L-027/11536(2017.01)
H01L-029/423
H01L-029/788
H01L-027/11521(2017.01)
출원번호
US-0919083
(2015-10-21)
등록번호
US-9728544
(2017-08-08)
우선권정보
KR-10-2014-0166698 (2014-11-26)
발명자
/ 주소
Yu, Tea Kwang
Kim, Yong Tae
Park, Jae Hyun
Yeom, Kyong Sik
출원인 / 주소
Samsung Electronics Co., Ltd.
대리인 / 주소
Harness, Dickey & Pierce, P.L.C.
인용정보
피인용 횟수 :
0인용 특허 :
45
초록▼
A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include seq
A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.
대표청구항▼
1. A method of manufacturing a semiconductor device, the method comprising: forming split gate structures, each including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate, the substrate including the cell region and a logic region adjacent to the cel
1. A method of manufacturing a semiconductor device, the method comprising: forming split gate structures, each including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate, the substrate including the cell region and a logic region adjacent to the cell region;sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region;removing the metal gate film from at least a portion of the cell region and the logic region;forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed;forming a gate electrode film on the logic region and the cell region; andforming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region by patterning the first and second gate insulating films, the gate electrode film, and a residue of the metal gate film. 2. The method of claim 1, wherein the logic region includes a first region adjacent to the cell region and a second region adjacent to the first region. 3. The method of claim 2, wherein the removing removes the metal gate film in the first region and the at least a portion of the cell region, while the metal gate film remains in the second region. 4. The method of claim 3, wherein a gate electrode formed in the first region and a gate electrode formed in the second region have different widths. 5. The method of claim 2, wherein the removing removes the metal gate film in the at least a portion of the cell region, while the metal gate film remains in the first region and the second region. 6. The method of claim 1, wherein the forming a plurality of gate electrodes includes: forming an erase gate electrode between the split gate structures; andforming a select gate electrode on an outside of each of the split gate structures. 7. The method of claim 1, wherein the removing comprises: performing a wet-etching process in which the metal gate film is removed in at least a portion of the logic region and the cell region, the wet-etch process using an etching solution containing an SC1 solution. 8. The method of claim 1, wherein the removing removes a portion of the metal gate film enclosing one end of the control gate electrode layer in an edge of the cell region. 9. The method of claim 1, wherein the first gate insulating film contains at least one of an aluminum oxide (Al2O3), a tantalum oxide (Ta2O3), a titanium oxide (TiO2), an yttrium oxide (Y2O3), a zirconium oxide (ZrO2), a zirconium silicon oxide (ZrSixOy), a hafnium oxide (HfO2), a hafnium silicon oxide (HfSixOy), a lanthanum oxide (La2O3), a lanthanum aluminum oxide (LaAlxOy), a lanthanum hafnium oxide (LaHfxOy), a hafnium aluminum oxide (HfAlxOy), and a praseodymium oxide (Pr2O3). 10. A method of manufacturing a semiconductor device having a split gate structure, the method comprising: forming a split gate structure on a substrate, the substrate including a cell region and a logic region;sequentially forming a first gate insulating film and a metal gate film on the split gate structures;removing a portion of the metal gate film;forming a second gate insulating film on the first gate insulating film;forming a gate electrode film on the cell region and the logic region; andforming an insulating layer, a first circuit element, a second circuit element, and a bit line on the substrate. 11. The method of claim 10, further comprising: injecting an impurity in a partial region of the substrate between the split gate structures to form a first impurity region. 12. The method of claim 11, further comprising: oxidizing the partial region of the substrate to form an oxide layer on the first impurity region. 13. The method of claim 12, wherein the oxide layer includes a central portion that is bulged. 14. The method of claim 10, wherein the removing a portion of the metal gate film completely removes the metal gate film in the cell region. 15. The method of claim 10, wherein the forming a split gate structure comprises: forming a floating gate electrode and a control gate electrode in the cell region of the substrate.
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