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[미국특허] Integrated apparatus for efficient removal of halogen residues from etched substrates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/306
  • H01L-021/02
  • H01L-021/67
  • H01L-021/687
출원번호 US-0201170 (2008-08-29)
등록번호 US-9735002 (2017-08-15)
발명자 / 주소
  • Kawaguchi, Mark Naoshi
  • Lo, Kin Pong
  • Hoogensen, Brett Christian
  • Wen, Sandy M.
  • Kim, Steven H.
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Patterson + Sheridan, LLP
인용정보 피인용 횟수 : 0  인용 특허 : 42

초록

A method and apparatus for removing volatile residues from a substrate are provided. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a load lock chamber and at least one processing chamber coupled to a transfer chamber, treating a subs

대표청구항

1. An apparatus for removing halogen-containing residues from a substrate, comprising: at least one etch chamber;a load lock chamber interfaced with a heat module that is adapted to heat a substrate disposed in the load lock chamber;a transfer chamber having a robot disposed therein that is adapted

이 특허에 인용된 특허 (42) 인용/피인용 타임라인 분석

  1. Nakajima Takahito (Yokohama JPX) Fukazawa Yuji (Yokohama JPX), Apparatus for subjecting a semiconductor substrate to a washing process.
  2. Janakiraman, Karthik; Suarez, Edwin C., Blocker plate by-pass for remote plasma clean.
  3. Kraus, Joseph Arthur; Strassner, James David, Dual wafer load lock.
  4. Angell David (Poughkeepsie NY) Radens Carl J. (Poughkeepsie NY), End-point detection.
  5. Wen-Hao Lo TW; Wen-Chyi Wang TW, HBr silicon etching process.
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  7. Jones Robert E. (Austin TX) Maniar Papu D. (Austin TX) Mogab C. Joseph (Austin TX), High-permittivity dielectric capacitor for use in a semiconductor device and process for making the same.
  8. Shawming Ma ; Guoqiang Xing ; Rahim Kavari ; Scott R. Summerfelt ; Tomoyuki Sakoda, Hydrogen-free contact etch for ferroelectric capacitor formation.
  9. Moslehi Mehrdad M. (Dallas TX), Low-temperature in-situ dry cleaning process for semiconductor wafer.
  10. Muralidhar Ramachandran ; Subramanian Chitra K. ; Madhukar Sucharita ; White Bruce E. ; Sadd Michael A. ; Zafar Sufi ; O'Meara David L. ; Nguyen Bich-Yen, Memory device that includes passivated nanoclusters and method for manufacture.
  11. Droopad Ravindranath ; Yu Zhiyi ; Ramdani Jamal, Method for fabricating a semiconductor structure with reduced leakage current density.
  12. Seung Ki Joo KR; Jang Sik Lee KR; Eung Chul Park KR, Method for fabricating ferroelectric thin film.
  13. Filipiak Stanley M. (Pflugerville TX), Method for forming a nitride layer using preheated ammonia.
  14. Ni, Tuqiang; Takeshita, Kenji; Choi, Tom; Lin, Frank Y.; Collison, Wenli, Method for improving uniformity and reducing etch rate variation of etching polysilicon.
  15. David Christopher Gilmer, Method for making a hafnium-based insulating film.
  16. Demmin, Timothy R.; Luly, Matthew H.; Fathimulla, Mohammed A., Method of etching and cleaning using fluorinated carbonyl compounds.
  17. Tsang Ling-Hsu,TWX ; Wu De-Yuan,TWX, Method of fabricating a deep trench capacitor.
  18. Ramdani Jamal ; Droopad Ravindranath ; Yu Zhiyi, Method of fabricating a semiconductor structure including a metal oxide interface.
  19. Inoue Naoya,JPX ; Hayashi Yoshihiro,JPX, Method of fabricating semiconductor device having memory capacitor including ferroelectric layer made of composite metal oxide.
  20. Imai Keitaro (Kawasaki JPX) Okano Haruo (Tokyo JPX) Aoyama Tomonori (Kawasaki JPX) Okayama Yasunori (Kawasaki JPX), Method of making semiconductor integrated-circuit capacitor.
  21. Lou Chine-Gie,TWX, Method of manufacturing a deep trench capacitor.
  22. Nakamura, Naoki, Method of manufacturing semiconductor device.
  23. Nakagawa Satoshi,JPX ; Ito Toyoji,JPX ; Bito Yoji,JPX ; Nagano Yoshihisa,JPX, Method of manufacturing semiconductor devices.
  24. Albert Lee ; Chris Ngai ; Christopher Bencher ; Tom Nowak, Method of processing a substrate in a processing chamber.
  25. Chebi, Robert; Hemker, David, Methods for reducing contamination of semiconductor substrates.
  26. Rodbell Kenneth P. (Poughkeepsie NY) Totta Paul A. (Poughkeepsie NY) White James F. (Newburgh NY), Multilayered intermetallic connection for semiconductor devices.
  27. Chen Jian (Santa Clara CA) Papanu James S. (San Rafael CA) Mak Steve S. Y. (Pleasanton CA) Ish-Shalom Carmel (Kiriat Motzkin ILX) Hsieh Peter (Sunnyvale CA) Lau Wesley G. (San Jose CA) Rhoades Charle, Passivating, stripping and corrosion inhibition of semiconductor substrates.
  28. Becknell, Alan Frederick; Buckley, Thomas James; Ferris, David; Pingree, Jr., Richard E.; Sakthivel, Palanikumaran; Srivastava, Aseem Kumar; Waldfried, Carlo, Plasma apparatus, gas distribution assembly for a plasma apparatus and processes therewith.
  29. Ha Heon-jae,KRX ; Son Hong-seong,KRX ; Hong Young-ki,KRX ; Song Jae-inh,KRX ; Park Chun-yong,KRX, Pre-treatment method performed on a semiconductor structure before forming hemi-spherical grains of capacitor storage node.
  30. Kaushik Vidya S. ; Nguyen Bich-Yen ; Adetutu Olubunmi O. ; Hobbs Christopher C., Process for forming a high-K gate dielectric.
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  34. Bosch, William Frederick, Semiconductor processing equipment having improved particle performance.
  35. Rivkin Michael ; Kaczorowski Ed, Single wafer load lock chamber for pre-processing and post-processing wafers in a vacuum processing system.
  36. Thomas J. Kropewnicki ; Jeremiah T. Pender ; Henry Fong ; Charles Peter Auglis ; Raymond Hung ; Hongqing Shan, Substrate cleaning process.
  37. Takashi Shigeoka JP; Takeshi Sakuma JP, Temperature measuring method, temperature control method and processing apparatus.
  38. Kenji Ando JP; Minoru Otani JP; Yasuyuki Suzuki JP; Toshiaki Shingu JP; Ryuji Biro JP; Hidehiro Kanazawa JP, Thin film production process and optical device.
  39. Ukai Katsumi (Fuchu JPX) Tsukada Tsutomu (Fuchu JPX) Ikeda Kouji (Fuchu JPX) Adachi Toshio (Fuchu JPX), Vacuum processing apparatus.
  40. Fuse Noboru (Yokohama JPX) Kitayama Hirofumi (Aikawa JPX) Hattori Hisashi (Tama JPX), Vertical wafer heat treatment apparatus having dual load lock chambers.
  41. Kroeker Tony R., Wafer cooling in a transfer chamber of a vacuum processing system.
  42. Chrisos John M. (Beverly MA) Fowler ; Jr. Bertram F. (Danvers MA) Muka Richard S. (Topsfield MA), Wafer handling apparatus.

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