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Semiconductor package with conductive clip 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/12
  • H01L-023/00
  • H01L-023/13
  • H01L-023/492
  • H01L-023/498
  • H01L-025/16
  • H01L-023/04
  • H01L-023/06
  • H01L-023/14
  • H01L-023/495
출원번호 US-0190466 (2016-06-23)
등록번호 US-9799623 (2017-10-24)
발명자 / 주소
  • Standing, Martin
출원인 / 주소
  • Infineon Technologies Americas Corp.
대리인 / 주소
    Shumaker & Sieffert, P.A.
인용정보 피인용 횟수 : 0  인용 특허 : 57

초록

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

대표청구항

1. A semiconductor package comprising: a conductive clip;a dielectric body mounted to said conductive clip;an integrated circuit mounted to said dielectric body;at least one output terminal electrically connected to said integrated circuit, and said dielectric body electrically insulating said at le

이 특허에 인용된 특허 (57)

  1. Beddingfield Stanley C., Bumped semiconductor device with alignment features and method for making the same.
  2. Covell ; II James H. ; Bolde Lannie R. ; Edwards David L. ; Goldmann Lewis S. ; Gruber Peter A. ; Toy Hilton T., Cast metal seal for semiconductor substrates and process thereof.
  3. Tokuda Masahide,JPX ; Kato Takeshi,JPX ; Itoh Hiroyuki,JPX ; Yagyu Masayoshi,JPX ; Fujita Yuuji,JPX ; Usami Mitsuo,JPX, Chip connection structure having diret through-hole connections through adhesive film and wiring substrate.
  4. Ariyoshi Shogo,JPX, Chip resistor having insulating body with a continuous resistance layer and semiconductor device.
  5. Standing, Martin; Schofield, Hazel Deborah, Chip scale surface mounted device and process of manufacture.
  6. Elsie A. Cabahug PH; Consuelo Tangpuz PH, Column ball grid array package.
  7. Davis Christopher ; Cheah Chuan ; Kinzer Daniel M., Commonly housed diverse semiconductor die.
  8. Cloud, Eugene H.; Farrar, Paul A., Die to die connection method and assemblies and packages including dice so connected.
  9. Hoffman Paul R. ; Popplewell James M. ; Braden Jeffrey S., Edge connectable metal package.
  10. Joseph Fjelstad, Expandable interposer for a microelectronic package and method therefor.
  11. Matsuda Shuichi,JPX ; Kata Keiichiro,JPX, Film carrier semiconductor device.
  12. Koors Mark Anthony ; Vajagich Robert ; Delheimer Charles I ; Brandenburg Scott David ; Oberlin Gary Eugene, Flip chip with backside electrical contact and assembly and method therefor.
  13. Yerman Alexander J. (Scotia NY) Neugebauer Constantine A. (Schenectady NY), Hermetic power chip packages.
  14. Bechtel Richard L. (Sunnyvale CA) Thomas Mammen (San Jose CA) Hively James W. (Sunnyvale CA), High density multichip package with interconnect structure and heatsink.
  15. Joshi Rajeev, High performance flip chip package.
  16. Granberg Helge O. (Phoenix AZ) Coffman Samuel L. (Scottsdale AZ), High power RF transistor assembly.
  17. Zeber Kenneth Arthur (Oakland Park FL), Integrated circuit chip formed from processing two opposing surfaces of a wafer.
  18. Newman Keith G. (Sunnyvale CA), Integrated circuit package lid.
  19. Peterson Robert K. ; Ozmat Burhan, Integrated circuit packaging method and the package.
  20. Djennas Frank ; Sterlin Wilhelm ; Joiner ; Jr. Bennett A., Low profile semiconductor device with like-sized chip and mounting substrate.
  21. Heilbronner,Heinrich; Stockmeier,Thomas, Low-inductance circuit arrangement for power semiconductor modules.
  22. Kajiwara,Ryoichi; Koizumi,Masahiro; Morita,Toshiaki; Takahashi,Kazuya; Kishimoto,Munehisa; Ishii,Shigeru; Hirashima,Toshinori; Takahashi,Yasushi; Hata,Toshiyuki; Sato,Hiroshi; Ookawa,Keiichi, MOSFET package.
  23. Valentine Richard J. (Mesa AZ), MOSFET “H”Switch circuit for a DC motor.
  24. Wiech, Jr., Raymond E., Method of fabricating complex microcircuit boards, substrates and microcircuits and the substrates and microcircuits.
  25. Glenn, Thomas P.; Gillett, Blake A., Method of making a semiconductor package having exposed metal strap.
  26. Kenji Sekine JP; Hiroji Yamada JP; Matsuo Yamasaki JP; Osamu Kagaya JP; Kiichi Yamashita JP, Multi-chip module structure having conductive blocks to provide electrical connection between conductors on first and second sides of a conductive base substrate.
  27. Fukuoka Yoshitaka,JPX, Multi-chip module, an electronic device, and production method thereof.
  28. Tagawa Tomohide (Kawanishi JPX) Takahashi Takashi (Kawanishi JPX) Kawakami Takayoshi (Itami JPX), Multiple-chip semiconductor device and a method of manufacturing the same.
  29. Pace Benedict G, Package for power semiconductor chips.
  30. Pike, Eric, Power delivery using an integrated heat spreader.
  31. Pike,Eric, Power delivery using an integrated heat spreader.
  32. Standing, Martin, Power semiconductor package.
  33. Standing, Martin, Power semiconductor package with conductive clip and related method.
  34. Standing, Martin, Process of fabricating a semiconductor package.
  35. Prost Roger,FRX, Pyroelectric sensor.
  36. Irons Robert Charles,GBX ; Billett Kevin Robert,GBX ; Evans Michael John,GBX, Semiconductor chips encapsulated within a preformed sub-assembly.
  37. Iwatani Shiro (Himeji JPX), Semiconductor device.
  38. Toshinori Hirashima JP; Munehisa Kishimoto JP; Toshiyuki Hata JP; Yasushi Takahashi JP, Semiconductor device and a method of manufacturing the same.
  39. Fukuizumi, Akira, Semiconductor device and method of manufacturing the same.
  40. Kagii,Hidemasa; Muto,Akira; Shimizu,Ichio; Arai,Katsuo; Sato,Hiroshi; Nakamura,Hiroyuki; Osaka,Masahiko; Nakajo,Takuya; Okawa,Keiichi; Oka,Hiroi, Semiconductor device and method of manufacturing the same.
  41. Yamaguchi Ichiro (Yokohama JPX), Semiconductor device having a ceramic package.
  42. Matsubara Hiroshi,JPX, Semiconductor device having a solder drawing layer.
  43. Moriguchi, Koji, Semiconductor device of surface-mounting type.
  44. Igarashi Kazumasa,JPX ; Nagasawa Megumu,JPX ; Tanigawa Satoshi,JPX ; Usui Hideyuki,JPX ; Yoshio Nobuhiko,JPX ; Ito Hisataka,JPX ; Okawa Tadao,JPX, Semiconductor device, production method thereof, and tape carrier for semiconductor device used for producing the semic.
  45. Joshi, Rajeev; Sapp, Steven, Semiconductor die package with improved thermal and electrical performance.
  46. Standing,Martin, Semiconductor package.
  47. Standing,Martin, Semiconductor package.
  48. Dahl Alex, Semiconductor package and method for increased thermal dissipation of flip-chip semiconductor package.
  49. Standing,Martin; Pavier,Mark; Clarke,Robert J.; Sawle,Andrew; McCartney,Kenneth, Semiconductor package fabrication.
  50. Standing, Martin, Semiconductor package with conductive clip.
  51. Hata, Toshiyuki; Sato, Hiroshi, Semiconductor packaging device comprising a semiconductor chip including a MOSFET.
  52. Majumdar Gourab (Toyko JPX) Iwagami Tooru (Toyko JPX) Noda Sukehisa (Toyko JPX), Semiconductor power module.
  53. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Single piece package for semiconductor die.
  54. Jimarez Miguel Angel ; Sarkhel Amit Kumar ; White Lawrence Harold, Solder hierarchy for chip attachment to substrates.
  55. Farnworth, Warren M.; Johnson, Mark S., Stereolithographic method and apparatus for packaging electronic components and resulting structures.
  56. Moline Daniel D. (Kuala Lumpur MYX), Surface mounting semiconductor device and method.
  57. Crane,Lawrence N.; Konarski,Mark M.; Yaeger,Erin K.; Torres Filho,Afranio; Krug,J. Paul; Tishkoff,Rebecca, Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith.
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