Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielec
Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
대표청구항▼
1. A method, comprising: forming an interconnect structure comprising a plurality of interconnect features disposed in a dielectric material over a substrate, wherein each of the plurality of interconnect features comprises an interconnect member and a via extending between the interconnect member a
1. A method, comprising: forming an interconnect structure comprising a plurality of interconnect features disposed in a dielectric material over a substrate, wherein each of the plurality of interconnect features comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material; andforming a through-silicon-via (TSV) structure laterally offset from the interconnect structure by: forming a first portion of the TSV structure with a first conductive material;forming a second portion of the TSV structure with a second conductive material;forming a first barrier layer, the first barrier layer having a first portion extending along and contacting a first sidewall of the first conductive material and a second portion extending along a second sidewall of the second conductive material; andforming a second barrier layer, the second barrier layer having a third portion extending along and contacting the second sidewall of the second conductive material and a fourth portion interposed between the first conductive material and the second conductive material;wherein the forming of the second portion of the TSV structure occurs simultaneously with forming a first interconnect feature of the plurality of interconnect features, wherein an interface between a first interconnect member of the first interconnect feature and a first via of the first interconnect feature is level with an interface between the first portion of the TSV structure and the second barrier layer. 2. The method of claim 1, wherein the dielectric material comprises a plurality of dielectric layers formed over the substrate. 3. The method of claim 2, wherein, for at least one of the plurality of interconnect features: the interconnect member extends through a first one of the plurality of dielectric layers;the via extends through a second one of the plurality of dielectric layers between the interconnect member and the conductive member; andthe conductive member extends through a third one of the plurality of dielectric layers. 4. The method of claim 3, wherein the second and third ones of the plurality of dielectric layers are disposed between the substrate and the first one of the plurality of dielectric layers. 5. The method of claim 3, wherein the forming of the interconnect structure further comprises forming a third barrier layer along internal surfaces of at least one opening defined in at least one of the plurality of dielectric layers substantially simultaneously with forming the second barrier layer. 6. The method of claim 1, wherein each interconnect member is formed as a portion of one of a plurality of metal layers formed in the dielectric material, wherein the plurality of metal layers includes at least a first metal layer, a second metal layer, and a third metal layer, and wherein the second portion of the TSV structure is formed with the second conductive material substantially simultaneously with forming the second metal layer. 7. The method of claim 1, wherein each interconnect member is formed as a portion of one of a plurality of metal layers formed in the dielectric material, wherein the plurality of metal layers includes at least a first metal layer, a second metal layer, and a third metal layer, and wherein the second portion of the TSV structure is formed with the second conductive material substantially simultaneously with forming one of the plurality of metal layers other than the second metal layer. 8. The method of claim 1, wherein the dielectric material substantially comprises a volume of dielectric gas. 9. The method of claim 1, wherein the forming of the TSV structure further comprises forming a TSV liner along internal surfaces of a TSV opening prior to forming the first portion of the TSV structure within the TSV opening. 10. The method of claim 1, wherein the first conductive material is same as the second conductive material. 11. A method, comprising: forming a first dielectric layer over a substrate;forming a plurality of electrically conductive plugs extending through the first dielectric layer;forming a second dielectric layer over the first dielectric layer and the plurality of electrically conductive plugs;forming a third dielectric layer over the second dielectric layer;forming a first dual-damascene structure comprising: a first interconnect extending through the third dielectric layer; anda first plurality of vias extending through the second dielectric layer between the first interconnect and the plurality of electrically conductive plugs;forming a fourth dielectric layer over the third dielectric layer and the first interconnect;forming a fifth dielectric layer over the fourth dielectric layer;forming a second dual-damascene structure comprising: a second interconnect extending through the fifth dielectric layer; anda second plurality of vias extending through the fourth dielectric layer between the second interconnect and the first interconnect; andforming a through-silicon-via (TSV) structure laterally offset from the first and second interconnects by: after forming the first, second, third, fourth, and fifth dielectric layers, forming a recess extending through the first, second, third, fourth, and fifth dielectric layers and into the substrate;filling a first portion of the recess with a first conductive material; andfilling a second portion of the recess with a second conductive material;wherein the filling of the second portion of the recess with the second conductive material occurs simultaneously with the forming of the second dual-damascene structure, and wherein a depth of the second portion of the recess relative to a top surface of the fifth dielectric layer is equal to a thickness of the fifth dielectric layer. 12. The method of claim 11, wherein the first and second conductive materials have substantially the same composition. 13. The method of claim 11, wherein the forming of the TSV structure further comprises forming a TSV liner along internal surfaces of the recess prior to filling the first portion of the recess with the first conductive material. 14. The method of claim 13, further comprising forming first and second barrier layers substantially simultaneously, including: forming the first barrier layer along internal surfaces of at least one opening defined in at least one of the first, second, third, fourth, and fifth dielectric layers, the at least one opening being different from the recess; andforming the second barrier layer along a surface of the first conductive material. 15. A method, comprising: forming a first metallization layer in a first dielectric layer over a substrate;forming a second dielectric layer over the first dielectric layer;after forming the second dielectric layer, etching a through substrate via (TSV) opening through the first and second dielectric layers and extending at least partially through the substrate, the etching occurring from a topmost portion of the TSV opening to a bottommost portion of the TSV opening in a single etch process;lining the TSV opening with a first barrier layer;partially filling the TSV opening with a first conductive material;after partially filling the TSV opening with the first conductive material, patterning the second dielectric layer to form a damascene opening therein, the damascene opening being laterally displaced from the TSV opening, wherein a depth of the damascene opening relative to a top surface of the second dielectric layer is substantially the same as a depth of the partially filled TSV opening relative to the top surface of the second dielectric layer;simultaneously lining the partially filled TSV opening and the damascene opening with a second barrier layer; andsimultaneously filling the partially filled TSV opening and the damascene opening with a second conductive material. 16. The method of claim 15, further comprising lining the TSV opening with a TSV liner before lining the TSV opening with the first barrier layer. 17. The method of claim 15, further comprising planarizing the second conductive material to be substantially planar with the top surface of the second dielectric layer. 18. The method of claim 15, further comprising: forming one or more additional metallization layers in one or more respective additional dielectric layers before forming the second dielectric layer, and etching through the one or more respective additional dielectric layers when etching the TSV opening. 19. The method of claim 18, wherein at least one of the one or more respective additional dielectric layers is a dielectric gas. 20. The method of claim 16, wherein the TSV liner comprises a dielectric material.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (12)
Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
Andry, Paul S.; Cooney, III, Edward C.; Lindgren, Peter J.; Ossenkop, Dorreen J.; Tsang, Cornelia K., Optimal tungsten through wafer via and process of fabricating same.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.