초록

A non-volatile memory element with thermal-assisted switching control is disclosed. The non-volatile memory element is disposed on a thermal inkjet resistor. Methods for manufacturing the combination and methods of using the combination are also disclosed.

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1. A non-volatile memory element with thermal-assisted switching control, comprising: a thermal element having a thickness of 95 nanometers, the thermal element to heat a resistive memory element; andthe resistive memory element disposed on the thermal elementwherein the thermal element heats the re

1. A non-volatile memory element with thermal-assisted switching control, comprising: a thermal element having a thickness of 95 nanometers, the thermal element to heat a resistive memory element; andthe resistive memory element disposed on the thermal elementwherein the thermal element heats the resistive memory element to different temperature regimes to perform different tasks. 2. The non-volatile memory element of claim 1, wherein the resistive memory element s a memristor. 3. The non-volatile memory element of claim 1, wherein the thermal element is a thermal inkjet resistor, the non-volatile memory element further comprising the thermal inkjet resistor, a passivation layer on the thermal inkjet resistor, and the resistive memory element on the passivation layer. 4. The non-volatile memory element of claim 3, in which the thermal inkjet resistor comprises a relatively low resistivity electrically conducting material disposed on a relatively high resistivity electrically conducting material. 5. The non-volatile memory element of claim 4, in which the thermal inkjet resistor is selected from the group consisting of AlCu on TaAl, AlCu on WSiN, AlCu on TaAlOx, AlCu on TiN, TaAl on TiN/AlCu, WSiN on TiN/AlCu, TaAlOx on TiN/AlCu, and TiN on TiN/AlCu. 6. The non-volatile memory element of claim 3, wherein the passivation layer is selected from the group consisting of silicon nitride, silicon carbide, and silicon dioxide. 7. The non-volatile memory element of claim 3, wherein the resistive memory element is a memristor having a structure that includes a bottom electrode, an active region, and a top electrode. 8. A method of manufacturing a multi-level programming non-volatile memory element; comprising disposing a non-volatile memory element on a thermal element, wherein: the non-volatile memory element has multiple states, each state associated with a temperature and an electrical bias;the thermal element heats a resistive memory element of the non-volatile memory element to multiple temperatures to place the resistive memory element in different states; andthe thermal element has a thickness of 95 nanometers. 9. The method of claim 8, comprising: providing a thermal inkjet resistor as the thermal element;forming a passivation layer on the thermal inkjet resistor; andforming the non-volatile on the passivation layer. 10. The method of claim 9, in which the thermal inkjet resistor comprises a relatively low resistivity electrically conducting material disposed on a relatively high resistivity electrically conducting material. 11. The method of claim 10, in which the thermal inkjet resistor is selected from the group consisting of AlCu on TaAl, AlCu on WSiN, AlCu on TaAlOx, AlCu on TiN, TaAl on TiN/AlCu, WSiN on TiN/AlCu, TaAlOx on TiN/AlCu, and TiN on TiN/AlCu. 12. The method of claim 9, wherein the passivation layer is selected from the group consisting of silicon nitride, silicon carbide, and silicon dioxide. 13. The method of claim 9, wherein the non-volatile memory element is a memristor having a structure that includes a bottom electrode, an active region, and a top electrode. 14. A method of operating a multi-level programming non-volatile memory element including a non-volatile memory element on a thermal element, the method including: providing the multi-level programming non-volatile memory element including the non-volatile memory element on the thermal element, which thermal element has a thickness of 95 nanometers;associating different temperatures and electrical biases with different logic states;energizing the thermal element to heat the non-volatile memory element to a pre-selected temperature; andstoring information in the non-volatile memory element. 15. The method of claim 14 in which the non-volatile memory element has multiple states, each associated with a combination of a temperature and electrical bias. 16. The non-volatile memory element of claim 1, wherein the thermal element is a dual-metal layer resistor. 17. The non-volatile memory element of claim 1, wherein: the thermal element is disposed under a crossbar array of non-volatile memory elements;top electrodes of resistive elements form columns of the crossbar array; andbottom electrodes of resistive elements form rows of the crossbar array. 18. The non-volatile memory element of claim 1, wherein: the thermal element heats the resistive memory element to a first temperature regime to control multi-cell applications:the thermal element heats the resistive memory element to a second temperature regime to repair a dead non-volatile memory element;the thermal element heats the resistive memory element to a third temperature regime to reset the non-volatile memory element; andthe thermal element heats the resistive memory element to a fourth temperature regime to electroform the non-volatile memory element. 19. The non-volatile memory element of claim 4, wherein: the relatively low resistivity electrically conducting material as a sheet resistance between 0.04 and 0.08 ohm/sq; andthe relatively high resistivity electrically conducting material has a sheet resistance between 30 and 120 ohm/sq.