Gate drive unit with analog measuring circuit
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02M-001/32
H03K-017/082
H03K-017/687
H02M-001/08
H02M-007/44
H03K-017/08
출원번호
US-0774446
(2014-03-26)
등록번호
US-9899999
(2018-02-20)
우선권정보
DK-2013 00190 (2013-03-27)
국제출원번호
PCT/DK2014/050072
(2014-03-26)
국제공개번호
WO2014/154221
(2014-10-02)
발명자
/ 주소
Rannestad, Bjørn
출원인 / 주소
KK Wind Solutions A/S
대리인 / 주소
Bodi Law LLC
인용정보
피인용 횟수 :
0인용 특허 :
6
초록▼
An intelligent gate drive unit and related method for controlling one or more semiconductor switches of one or more power modules, the intelligent gate drive unit comprises at least a gate driver and an analog measuring circuit, wherein the gate driver facilitates control of the one or more semicond
An intelligent gate drive unit and related method for controlling one or more semiconductor switches of one or more power modules, the intelligent gate drive unit comprises at least a gate driver and an analog measuring circuit, wherein the gate driver facilitates control of the one or more semiconductor switches and wherein the analog measuring circuit facilitates measuring the switch voltage when the one or more semiconductor switches are in a conducting mode.
대표청구항▼
1. An intelligent gate drive unit for controlling at least two semiconductor switches in a half-bridge configuration between an upper DC terminal and a lower DC terminal of a power module, the intelligent gate drive unit comprising: at least two gate drivers, each configured for controlling the swit
1. An intelligent gate drive unit for controlling at least two semiconductor switches in a half-bridge configuration between an upper DC terminal and a lower DC terminal of a power module, the intelligent gate drive unit comprising: at least two gate drivers, each configured for controlling the switching of one of the at least two semiconductor switches;an analog measuring circuit configured to measure an analog voltage measurement of at least one of the at least two semiconductor switches in real time while the at least one of the at least two semiconductor switches is in a conducting mode, whereinthe reference potential of the analog measuring circuit is the midpoint of the half-bridge such that the analog measuring circuit is configured for measuring the analog voltage of at least one of the at least two semiconductor switches between the midpoint of the half-bridge configuration and the upper DC terminal or between the midpoint of the half-bridge configuration and the lower DC terminal, and whereinthe analog measuring circuit is further configured to output the analog voltage to a data processor, and further whereinthe data processor is configured for receiving a signal which represents the output current of the half-bridge configuration; such thatthe processor is configured to calculate an estimated current temperature of at least one of the at least two semiconductor switches based on the analog voltage measurement taken during the conducting mode and based on the signal representing the output current of the half-bridge configuration. 2. The intelligent gate drive unit according to claim 1, wherein the analog measuring circuit further facilitates measuring the switch voltage in a switching mode. 3. The intelligent gate drive unit according to claim 1, wherein the analog measuring circuit further facilitates measuring the switching voltage in a non-conducting mode. 4. The intelligent gate drive unit according to claim 3, wherein said analog measuring circuit includes means such as a semiconductor device for blocking the high voltage across the semiconductor switch, which preferably is an IGBT, during the non-conducting mode. 5. The intelligent gate drive unit according to claim 1, wherein the measurements from the analog measuring circuit include measuring power module output current and/or DC-link voltage. 6. The intelligent gate drive unit according to claim 1, wherein the intelligent gate drive unit further comprises a data processor facilitating calculation of semiconductor switch junction temperature at the intelligent gate drive unit. 7. The intelligent gate drive unit according to claim 1, wherein the one or more power modules is/are part of an inverter or part of a brake chopper. 8. The intelligent gate drive unit according to claim 1, wherein the intelligent gate drive unit is configured for controlling the load conducted by the individual semiconductor switches. 9. The intelligent gate drive unit according to claim 1, wherein a data processor facilitates time synchronization between measurements of the switch voltage and an output current of a power module and/or measurements of a DC-link voltage and an output current of the power module. 10. The intelligent gate drive unit according to claim 1, wherein the measurements from the analog measuring circuit facilitate estimation of at least one or more of the list comprising: junction temperature of the semiconductor switch, baseplate temperature of the semiconductor switch, a brake chopper resistor temperature, fatigue level of the semiconductor switch, fatigue level of the brake chopper resistor, end of lifetime of the semiconductor switch and/or end of lifetime of the brake chopper resistor. 11. The intelligent gate drive unit according to claim 1, wherein the intelligent gate drive unit facilitates overcurrent protection and/or over temperature protection of the one or more semiconductor switches. 12. The intelligent gate drive unit according to claim 1, wherein the switching behavior of the semiconductor switch is configured to be controlled by means of one or more gate resistors, wherein the value of said one or more gate resistors is changed based on measured operational parameters controlling one or more gate resistor switches. 13. The intelligent gate drive unit according to claim 1, wherein overvoltage protection of the semiconductor switch is configured to be disabled by means of an active clamping switch based on measurement of operational parameters. 14. The intelligent gate drive unit according to claim 1, wherein overcurrent protection of the semiconductor switch is configured to be disabled by means of a saturation switch based on measurements of operational parameters. 15. The intelligent date drive unit according to claim 14, wherein the control performed by the intelligent gate driver at least includes one or more of the list comprising: enable an active clamping function, disable the active clamping function, change value of a gate resistor, load sharing in power modules, turn on the semiconductor switch, turn off the semiconductor switch. 16. The intelligent gate drive unit according to claim 1, wherein the intelligent gate drive unit is configured to communicate with a superior control system in order to obtain a desired switching pattern and thereby a desired output from the power modules. 17. The intelligent gate drive unit according to claim 1, wherein control performed by the intelligent gate drive unit is made based on measurements obtained from the analog measuring circuit and/or from data received from a superior control system. 18. A printed circuit board comprising an intelligent gate drive unit according to claim 1 for controlling one or more semiconductor switches of one or more power modules. 19. A wind turbine comprising one or more power modules of which semiconductor switches are controlled by an intelligent gate drive unit as described in claim 1. 20. The intelligent gate driver unit according to claim 1, wherein the data processor is part of a superior control system. 21. The intelligent gate driver unit according to claim 1, wherein the estimated current temperature is utilized by the processor for diagnosing a health status of at least one of the at least two semiconductor switches. 22. An intelligent gate drive unit for controlling at least two semiconductor switches in a half-bridge configuration between an upper DC terminal and a lower DC terminal a power module in a half-bridge configuration, the intelligent gate drive unit comprising: at least two gate drivers each of which configured for controlling the switching of one of the at least two semiconductor switches;an analog measuring circuit configured to measure an analog voltage of the one of the at least two semiconductor switches in real time while the one of the at least two semiconductor switches are in a conducting mode;wherein the reference potential of the analog measuring circuit is the midpoint of the half-bridge configuration such that the analog measuring circuit is configured for measuring the analog voltage of at least one of the at least two semiconductor switches between the midpoint of the half-bridge configuration and upper DC terminal or between the midpoint of the half-bridge and the lower DC terminal, and wherein the analog measuring circuit is further configured to output the analog voltage to a data processor; andwherein the processor is configured to calculate an estimated current temperature of at least one of the at least two semiconductor switches from the analog voltage, and wherein said estimated current temperature is utilized by the processor for diagnosing a health status of at least one of the at least two semiconductor switches.
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이 특허에 인용된 특허 (6)
Meyer Helmut (Dossenheim DEX), Converter with intermediate d.c. circuit.
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