Systems and methods for controlling multi-level diode-clamped inverters using space vector pulse width modulation (SVPWM)
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02J-003/12
G05F-001/00
H02M-007/487
H02J-009/06
H02M-003/04
출원번호
US-0493978
(2017-04-21)
등록번호
US-9912251
(2018-03-06)
발명자
/ 주소
Mondal, Subrata K
출원인 / 주소
INERTECH IP LLC
대리인 / 주소
Carter, Deluca, Farrell & Schmidt, LLP
인용정보
피인용 횟수 :
0인용 특허 :
81
초록▼
Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then select
Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.
대표청구항▼
1. A control system for a multi-level inverter, comprising: a digital logic circuit comprising: a plurality of digital logic comparators including a first comparator and a second comparator;a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality
1. A control system for a multi-level inverter, comprising: a digital logic circuit comprising: a plurality of digital logic comparators including a first comparator and a second comparator;a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; anda plurality of AND gates including an AND gate, the AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator;a digital up/down counter coupled to first inputs of the plurality of comparators, the up/down counter counting from 0 to Ts/2 and then from Ts/2 to 0, where Ts is a sampling period; anda processor and memory configured to: identify a sector location based on an actual angle of a reference voltage vector;convert the actual angle into a converted angle located in a first sector;identify a reference region location based on the magnitude of the reference voltage vector and the converted angle in the first sector;select a switching sequence and turn-on time values based on the corresponding actual region location and actual sector;transmit turn-on time values to second inputs of the plurality of comparators; andprovide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter. 2. The control system of claim 1, wherein the logic circuit is a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). 3. The control system of claim 1, wherein the processor and memory are implemented by a digital signal processor (DSP). 4. The control system of claim 1, wherein the number of the plurality of comparators and the number of the plurality of inverters is one less than the number of levels of the multi-level inverter. 5. The control system of claim 4, wherein the number of the plurality of AND gates is one less than the number of the plurality of comparators. 6. The control system of claim 1, wherein the processor and memory are further configured to: convert the reference voltage vector and the converted angle into X and Y coordinate point values in first sector; andidentify a region location based on the X and Y coordinate point values. 7. The control system of claim 6, wherein the identifying a region location includes comparing the X and Y coordinate point values to segments of triangles, which represent regions, in a vector space. 8. The control system of claim 6, wherein the turn-on time values and switching sequence are predetermined for each sector and region, and stored in a look-up table stored in memory. 9. The control system of claim 1, wherein the sector locations are sectors A-F and the first sector is sector A. 10. The control system of claim 1, wherein the multi-level inverter is a five-level inverter, wherein the plurality of comparators further include a third comparator and a fourth comparator,wherein the plurality of inverters further include a second inverter, a third inverter, and a fourth inverter,wherein the plurality of AND gates further include a second AND gate, and a third AND gate,wherein a first input of the second AND gate is coupled to the output of the second inverter and a second input of the second AND gate is coupled to the output of the third comparator,wherein a first input of the third AND gate is coupled to the output of the third inverter and a second input of the third AND gate is coupled to the output of the fourth comparator, andwherein the output of the first comparator, the outputs of the plurality of AND gates, and the output of the fourth inverter provide the switching signals for an IGBT driver of a five-level inverter. 11. The control system of claim 1, wherein the multi-level inverter is a four-level inverter, wherein the plurality of comparators further include a third comparator,wherein the plurality of inverters further include a second inverter and a third inverter,wherein the plurality of AND gates further include a second AND gate,wherein a first input of the second AND gate is coupled to the output of the second inverter and a second input of the second AND gate is coupled to the output of the third comparator,wherein the output of the first comparator, the outputs of the plurality of AND gates, and the output of the third inverter provide the switching signals. 12. A method of controlling a multi-level inverter, comprising: identifying a sector location based on an actual angle of a reference voltage vector;converting the actual angle into a converted angle located in a first sector;identifying a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector;selecting a switching sequence and a plurality of turn-on time values based on the corresponding region location in actual sector of reference voltage vector;transmitting the turn-on time values to second inputs of the plurality of comparators to generate switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter;comparing each of the plurality of turn-on signals to a digital up/down counter signal to obtain a plurality of comparison signals including a first comparison signal and a second comparison signal;inverting the plurality of comparison signals to obtain a plurality of inverted signals including a first inverted signal; andperforming a logical AND operation on the first inverted signal and the second comparison signal to obtain a switching signal, which is transmitted to a gate driver for driving a power transistor of the multi-level inverter. 13. The method of claim 12, further comprising: converting the reference voltage vector and the converted angle into X and Y coordinate point values; andidentifying a region location based on the X and Y coordinate point values. 14. The method of claim 13, wherein the identifying a region location includes comparing the X and Y coordinate point values to segments of triangles, which represent regions, in a vector space. 15. The method of claim 13, wherein the turn-on time values and switching sequences are predetermined for each sector and region, and stored in a look-up table stored in memory. 16. The method of claim 12, wherein the first comparison signal is a first switching signal, wherein the logical AND operation is performed on the first inverted signal and the second comparison signal to obtain a second switching signal,wherein the plurality of comparison signals further include a third comparison signal and a fourth comparison signal,wherein the plurality of inverted signals further include a second inverted signal, a third inverted signal, and a fourth inverted signal,wherein the method further comprises: performing a second logical AND operation on the second inverted signal and the third comparison signal to obtain a third switching signal; andperforming a second logical AND operation on the second inverted signal and the third comparison signal to obtain a fourth switching signal, andwherein the fourth inverted signal is a fifth switching signal. 17. The method of claim 16, wherein the first switching signal corresponds to either a P2 or N2 switching state, wherein the second switching signal corresponds to either a P1 or N1 switching state,wherein the third switching signal corresponds to an O switching state,wherein the fourth switching signal corresponds to either an N1 or P1 switching state, andwherein the fifth switching signal corresponds to either an N2 or P2 switching state. 18. An energy storage system comprising: an energy storage device;a DC-DC converter coupled to the energy storage device;a multi-level inverter coupled to the DC-DC converter; anda controller for the multi-level inverter, the controller comprising: a digital logic circuit comprising: a plurality of comparators including a first comparator and a second comparator;a plurality of inverters coupled to respective outputs of a respective plurality of comparators, the plurality of inverters including a first inverter; anda plurality of AND gates including a first AND gate, the first AND gate having a first input and a second input, the first input coupled to the output of the first inverter and the second input coupled to the output of the second comparator;a counter coupled to first inputs of the plurality of comparators; anda processor and memory configured to: identify a sector location based on an actual angle of a reference voltage vector;convert the actual angle into a converted angle located in a first sector;identify a region location based on the magnitude of the reference voltage vector and the converted angle in the first sector;select a switching sequence and turn-on signal values based on the corresponding region and actual reference voltage vector location;transmit turn-on signal values to second inputs of the plurality of comparators; andprovide the output of the first comparator, the outputs of the plurality of AND gates, and the output of a last inverter of the plurality of inverters as switching signals, which are transmitted to gate drivers for driving power transistors of the multi-level inverter.
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