Matrix type integrated circuit with fault isolation capability
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-031/02
H01L-027/146
G01R-031/26
H04N-005/32
H04N-005/367
H04N-005/376
출원번호
US-0007312
(2016-01-27)
등록번호
US-9947712
(2018-04-17)
발명자
/ 주소
Roos, Pieter Gerhard
출원인 / 주소
VAREX IMAGING CORPORATION
대리인 / 주소
Su IP Consulting
인용정보
피인용 횟수 :
1인용 특허 :
4
초록▼
Technology is described for selectively disconnecting a communal module (e.g., horizontal power and signal distribution network) from conductive traces (e.g., vertical columns) that are coupled to cell elements. In one example, a matrix type integrated circuit includes a two dimensional (2D) array o
Technology is described for selectively disconnecting a communal module (e.g., horizontal power and signal distribution network) from conductive traces (e.g., vertical columns) that are coupled to cell elements. In one example, a matrix type integrated circuit includes a two dimensional (2D) array of cell elements, a plurality of conductive traces, a communal module, and a plurality of switches. Each cell element in the 2D array provides a similar function. The plurality of conductive traces is substantially parallel to a first axis of the 2D array. Each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace. The communal module is configured to provide distribution of at least one electrical signal to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis.
대표청구항▼
1. A matrix type integrated circuit, comprising: a two dimensional (2D) array of cell elements, wherein each cell element provides a similar function;a plurality of conductive traces substantially parallel to a first axis of the 2D array, wherein each conductive trace is coupled to a conductive inte
1. A matrix type integrated circuit, comprising: a two dimensional (2D) array of cell elements, wherein each cell element provides a similar function;a plurality of conductive traces substantially parallel to a first axis of the 2D array, wherein each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace;a communal module configured to provide distribution of at least one electrical signal to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis; anda plurality of switches, wherein each switch is configured to selectively disconnect the communal module from one of the conductive traces. 2. The matrix type integrated circuit of claim 1, wherein the matrix integrated circuit is a complementary metal-oxide-semiconductor (CMOS) image sensor and each cell element includes a photodiode for a pixel. 3. The matrix type integrated circuit of claim 2, wherein the CMOS image sensor is an X-ray image sensor that includes a scintillator layer that coverts radiation into light photons for the photodiodes. 4. The matrix type integrated circuit of claim 1, wherein the switch is selected from a group consisting of tri-state logic and an enable buffer. 5. The matrix type integrated circuit of claim 1, wherein a length of each of the at least two of the plurality of conductive traces extends beyond a reticle boundary. 6. The matrix type integrated circuit of claim 1, wherein a length of each of the at least two of the plurality of conductive traces is greater than 50 millimeters (mm). 7. The matrix type integrated circuit of claim 1, wherein: the plurality of conductive traces include at least one power trace, at least one digital signal trace, and at least one analog signal trace coupled to each cell element;the communal module is configured to provide distribution of a power signal to the cell elements in the 2D array via the at least one power trace, anda control signal to the cell elements in the 2D array via the at least one digital signal trace, anda reference signal to the cell elements in the 2D array via the at least one analog signal trace; andthe plurality of switches includes at least one power switch, at least one control switch, and at least one reference switch, and the plurality of switches are controlled by an enable signal, and the at least one power switch is coupled to the at least one power trace, the at least one control switch is coupled to the at least one digital signal trace, and the at least one reference switch is coupled to the at least one analog signal trace. 8. The matrix type integrated circuit of claim 1, further comprising: disable logic to selectively disable the plurality of switches, wherein the disable logic includes a programming port that allows external access to the matrix type integrated circuit for programming the disable logic. 9. The matrix type integrated circuit of claim 8, wherein the disable logic is selected from a group consisting of a serial control register, a shift register, an address register, a programmable read-only memory (PROM), a non-volatile random-access memory (NVRAM), and combinations thereof. 10. The matrix type integrated circuit of claim 1, further comprising: a plurality of fault detectors, wherein each fault detector is coupled to at least one of the plurality of conductive traces and is configured to detect a fault condition on the coupled conductive traces and generate a fault status signal when the fault condition occurs. 11. The matrix type integrated circuit of claim 1, wherein each fault detector includes a current sense amplifier, and the fault condition is selected from a group consisting of an excessive supply current on at least one of the conductive traces, a short circuit between at least two of the conductive traces, and combinations thereof. 12. The matrix type integrated circuit of claim 1, further comprising: a fault status module coupled to the plurality of the fault detectors, wherein the fault status module is configured to capture the fault status signal for each fault and the fault status module includes a status port that allows external access to the matrix type integrated circuit for reading the captured fault status signals from the plurality of fault detectors, and wherein the fault status module is selected from a group consisting of a serial register, a shift register, a multiplexer, a non-volatile random-access memory (NVRAM), and combinations thereof. 13. The matrix type integrated circuit of claim 12, wherein the fault status module includes a fault detector selector input to read the fault status signal of a specified fault detector from the status port. 14. The matrix type integrated circuit of claim 12, further comprising: disable logic configured to selectively disable the plurality of switches, wherein the disable logic includes an internal programming input; andan automatic fault isolator configured to program the disable logic via the internal programming input based on the fault status signal for each fault detector obtained by the fault status module. 15. The matrix type integrated circuit of claim 14, wherein the automatic fault isolator includes circuitry selected from a group consisting of a field-programmable gate array (FPGA), a state machine, a microprocessor, and combinations thereof. 16. The matrix type integrated circuit of claim 14, wherein the automatic fault isolator includes a fault detector selector output, a fault status input, and a disable logic program output, and the fault detector selector output is coupled to a fault detector selector input of the fault status module that is configured for selecting a specified fault detector,the fault status input is coupled to the status port of the fault status module that is configured for reading the fault status signal of the specified fault detector, andthe disable logic program output is coupled to the internal programming input of the disable logic to selectively disable the plurality of switches based on the fault conditions detected by the plurality of fault detectors. 17. The matrix type integrated circuit of claim 14, wherein the automatic fault isolator includes a programming port that allows external access to the matrix type integrated circuit for programming the automatic fault isolator. 18. A method of selectively disabling a plurality of switches coupled to a communal module for a matrix type integrated circuit, the method comprising: providing a two dimensional (2D) array of cell elements that includes: a plurality of conductive traces substantially parallel to a first axis of the 2D array, wherein each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace, and wherein each cell element provides a similar function,a communal module configured to provide distribution of electrical signals to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis, anda plurality of switches, wherein each switch is configured to selectively disconnect the communal module from one of the conductive traces; andselectively disabling at least one of the plurality of switches coupled to the communal module from at least one of the conductive traces. 19. The method of claim 18, further comprising: detecting a fault condition on at least one of the conductive traces using a plurality of fault detectors, wherein each fault detector is coupled to at least one of the plurality of conductive traces, and the fault condition is selected from a group consisting of an excessive supply current on at least one of the conductive traces, a short circuit between at least two of the conductive traces, and combinations thereof; andgenerating a fault status signal when the fault condition occurs. 20. The method of claim 19, further comprising: registering, using a fault status module, a fault status bit for each fault detector generating the fault status signal. 21. The method of claim 19, further comprising: based on the fault status signals from the plurality of fault detectors, automatically programming selected switches to disable the communal module from the conductive traces. 22. At least one non-transitory machine readable storage medium comprising a plurality of instructions adapted to be executed to implement the method of claim 19. 23. A matrix type integrated circuit, comprising: a two dimensional (2D) array of cell elements arranged in vertical columns and horizontal rows, wherein each cell element provides a similar function;a plurality of vertical traces arranged in each column of the 2D array, wherein each vertical trace is coupled to a conductive interconnect of cell elements within each column;a communal module configured to provide distribution of electrical signals to the cell elements in the 2D array via at least two vertical traces for each column; anda plurality of switches, wherein each switch is configured to selectively disconnect the communal module from one of the vertical traces. 24. The matrix type integrated circuit of claim 23, wherein the communal module includes a plurality of horizontal traces, wherein each switch is coupled to one of the plurality of horizontal traces. 25. The matrix type integrated circuit of claim 23, further comprising: disable logic to selectively disable the plurality of switches, wherein the disable logic includes a programming port external to a package of the matrix type integrated circuit for programming the disable logic.
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이 특허에 인용된 특허 (4)
Krug Heinz (c/o Akademie Meru ; Station 24 NL-6063 Vlodrop NLX), Circuit arrangement for testing integrated circuit components.
Rostoker Michael D. (San Jose CA) Dangelo Carlos (San Jose CA) Koford James (San Jose CA) Fulcher Edwin (Palo Alto CA), Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies.
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