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An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plu

An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.

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1. An operating method of a memory device supporting command bus training, the operating method comprising: entering into a mode of the command bus training;receiving a clock signal, chip selection signal and a first command/address signal;generating a plurality of internal clock signals by dividing

1. An operating method of a memory device supporting command bus training, the operating method comprising: entering into a mode of the command bus training;receiving a clock signal, chip selection signal and a first command/address signal;generating a plurality of internal clock signals by dividing the clock signal;generating a plurality of internal chip selection signals by latching the chip selection signal according to the plurality of internal clock signals;generating a second command/address signal by encoding the first command/address signal based on the plurality of internal chip selection signals; andoutputting the second command/address signal. 2. The operating method of claim 1, wherein generating the second command/address signal comprises generating the second command/address signal by differently encoding the first command/address signal according to voltage levels of the plurality of internal chip selection signals. 3. The operating method of claim 2, wherein the plurality of internal clock signals comprise first and second internal clock signals each having the same frequency and a phase difference of 180 degrees with respect to each other, and wherein the plurality of internal chip selection signals comprise first and second internal chip selection signals generated by latching the chip selection signal according to the first and second internal clock signals, respectively. 4. The operating method of claim 3, wherein generating the second command/address signal comprises: encoding the first command/address signal by a first encoding method when only the first internal chip selection signal is activated,encoding the first command/address signal by a second encoding method when only the second internal chip selection signal is activated,encoding the first command/address signal by a third encoding method when the first and second internal chip selection signals are activated in this stated order, andencoding the first command/address signal by a fourth encoding method when the second and first internal chip selection signals are activated in this stated order. 5. The operating method of claim 2, wherein generating the second command/address signal comprises generating the second command/address signal by inverting or non-inverting at least one bit of the first command/address signal according to the voltage levels of the plurality of internal chip selection signals. 6. A command bus training method in a system in which a command/address signal and a clock signal are provided to a memory device from a memory controller, the command bus training method comprising: generating a plurality of internal clock signals in the memory device by dividing the clock signal;transmitting a first command/address signal by the memory controller;transmitting a chip selection signal by the memory controller, the chip selection signal having an adjustable delay with respect to each of the internal clock signals;generating a plurality of internal chip selection signals in the memory device by latching the chip selection signal according to the plurality of internal clock signals;generating and transmitting by the memory device, a second command/address signal by encoding the first command/address signal based on the plurality of internal chip selection signals; anddetermining a delay of the chip selection signal based on the first and second command/address signals in the memory controller. 7. The command bus training method of claim 6, wherein determining the delay of the chip selection signal comprises: generating a plurality of decoded signals by decoding the second command/address signal;comparing each of the plurality of decoded signals to the first command/address signal; anddetermining the delay of the chip selection signal based on a plurality of comparison results corresponding to the adjustable delay of the chip selection signal. 8. The command bus training method of claim 7, wherein generating the plurality of decoded signals comprises generating the plurality of decoded signals by inverting or non-inverting at least one bit of the second command/address signal. 9. The command bus training method of claim 6, wherein determining the delay of the chip selection signal comprises: generating a plurality of second encoded signals by encoding the first command/address signal;comparing each of the plurality of second encoded signals to the second command/address signal; anddetermining the delay of the chip selection signal based on a plurality of comparison results corresponding to the adjustable delay of the chip selection signal. 10. The command bus training method of claim 9, wherein generating the plurality of second encoded signals comprises generating the plurality of second encoded signals by inverting or non-inverting at least one bit of the first command/address signal. 11. The command bus training method of claim 6, wherein generating and transmitting the second command/address signal comprises generating the second command/address signal by differently encoding the first command/address signal according to levels of the plurality of internal chip selection signals. 12. The command bus training method of claim 11, wherein generating the second command/address signal comprises generating the second command/address signal by inverting or non-inverting at least one bit of the first command/address signal according to the levels of the plurality of internal chip selection signals. 13. The command bus training method of claim 11, wherein the plurality of internal clock signals comprise first and second internal clock signals each having the same frequency and a phase difference of 180 degrees with respect to each other, and wherein the plurality of internal chip selection signals comprise first and second internal chip selection signals generated by latching the chip selection signal according to the first and second internal clock signals, respectively. 14. The command bus training method of claim 13, wherein generating and transmitting the second command/address signal comprises: encoding the first command/address signal by a first encoding method when only the first internal chip selection signal is activated,encoding the first command/address signal by a second encoding method when only the second internal chip selection signal is activated,encoding the first command/address signal by a third encoding method when the first and second internal chip selection signals are activated in this stated order, andencoding the first command/address signal by a fourth encoding method when the second and first internal chip selection signals are activated in this stated order. 15. The command bus training method of claim 14, wherein determining the delay of the chip selection signal comprises determining a median value of delays of the chip selection signal corresponding to the second command/address signal encoded by the first encoding method, or a median value of the chip selection signal corresponding to the second command/address signal encoded by the second encoding method, as the delay of the chip selection signal. 16. A method of command bus training for a semiconductor device, the method comprising: receiving a first command/address signal, and a clock signal having a first frequency;generating internal clock signals based on the clock signal, each of the internal clock signals having a second frequency and different phases with respect to each other, wherein the second frequency is smaller than the first frequency;a) receiving a chip selection signal having variable delays with respect to each of the internal clock signals;b) generating internal chip selection signals by latching the chip selection signal based on the internal clock signals;c) generating a second command/address signal by encoding the first command/address signal based on the internal chip selection signals; anddetermining a delay of the chip selection signal based on the first and second command/address signals. 17. The method of claim 16, wherein determining the delay of the chip selection signal comprises: d) generating decoded signals by decoding the second command/address signal;e) comparing the first command/address signal to the decoded signals;repeating a), b), c), d), and e) with a different delay of the variable delays of the chip selection signal; anddetermining the delay of the chip selection signal based on the comparison results. 18. The method of claim 16, wherein determining the delay of the chip selection signal comprises: d) generating second encoded signals by encoding the first command/address signal;e) comparing the second command/address signal to the second encoded signals;repeating a), b), c), d), and e) with a different delay of the variable delays of the chip selection signal; anddetermining the delay of the chip selection signal based on the comparison results. 19. The method of claim 16, wherein the internal clock signals comprise first and second internal clock signals, wherein the internal chip selection signals comprise first and second internal chip selection signals generated by latching the chip selection signal based on the first and second internal clock signals, respectively,wherein the second command/address signal includes a first set of command/address signals and a second set of command/address signals,wherein, when only one of the first and second internal chip selection signals is activated the first and second sets of command/address signals are either non-inverted or inverted, andwherein, when both of the first and second internal chip selection signals are activated at a different time only one set of the first and second sets of command/address signals is either non-inverted or inverted. 20. The method of claim 19, wherein when both of the first and second internal chip selection signals are activated at a different time the first set of command/address signals is generated based on a first activated signal of the first and second internal chip selection signals, and the second set of command/address signals is generated based on a second activated signal of the first and second internal chip selection signals.