Semiconductor device and methods for forming a semiconductor device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/265
H01L-029/36
H01L-029/66
H01L-029/78
H01L-029/861
H01L-029/06
H01L-029/08
H01L-029/10
출원번호
US-0297914
(2016-10-19)
등록번호
US-9960044
(2018-05-01)
우선권정보
DE-10 2015 117 821 (2015-10-20)
발명자
/ 주소
Laven, Johannes Georg
Schulze, Hans-Joachim
Schustereder, Werner
출원인 / 주소
Infineon Technologies AG
대리인 / 주소
Murphy, Bilak & Homiller, PLLC
인용정보
피인용 횟수 :
0인용 특허 :
3
초록▼
A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the
A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate. The method further includes controlling a temperature of the semiconductor substrate during the implantation of the doping ions so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the doping ions. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. The lower target temperature limit is equal to a target temperature minus 30° C., and the target temperature is higher than 80° C.
대표청구항▼
1. A method for forming a semiconductor device, the method comprising: implanting doping ions into a semiconductor substrate, wherein a deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° du
1. A method for forming a semiconductor device, the method comprising: implanting doping ions into a semiconductor substrate, wherein a deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate; andcontrolling a temperature of the semiconductor substrate during the implantation of the doping ions so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the doping ions,wherein the target temperature range reaches from a lower target temperature limit to an upper target temperature limit, wherein the lower target temperature limit is equal to a target temperature minus 30° C., wherein the target temperature is higher than 80° C. 2. The method of claim 1, wherein the main crystal direction of the semiconductor substrate is a direction of a crystalline structure of the semiconductor substrate at which ion channeling of at least 70% of the implanted doping ions occurs in the semiconductor substrate. 3. The method of claim 1, wherein the main crystal direction of the semiconductor substrate is a direction of a crystalline structure of the semiconductor substrate at which the doping ions implanted into the semiconductor substrate encounter minimal scattering or stopping power in comparison to other directions of the crystalline structure of the semiconductor substrate. 4. The method of claim 1, wherein the main crystal direction of the semiconductor substrate is a [110] or [111] direction of a diamond cubic crystal lattice of the semiconductor substrate. 5. The method of claim 1, further comprising controlling an angle between the main direction of the doping ion beam and a main lateral surface of the semiconductor substrate during the implanting of the doping ions into the semiconductor substrate, such that an angle of incidence of the doping ion beam deviates from the main crystal direction by less than ±0.5°. 6. The method of claim 1, wherein the doping ions are implanted into the semiconductor substrate at an implantation energy of greater than 100 keV. 7. The method of claim 1, wherein the temperature of the semiconductor substrate is controlled during the implantation of the doping ions such that more than 30% of the doping ions implanted into the semiconductor substrate are activated. 8. The method of claim 1, wherein the doping ions are implanted into the semiconductor substrate at an implantation dose of greater than 1*1014 doping ions per cm2. 9. The method of claim 8, wherein the temperature of the semiconductor substrate is controlled to within the target temperature range such that amorphisation of the semiconductor substrate begins at a temperature above 50° C. 10. The method of claim 1, wherein the target temperature is above 200° C. 11. The method of claim 1, wherein the implantation of the doping ions is performed such that at least one device doping region comprising a maximal doping concentration of larger than 1*1018 dopant atoms per cm3 is formed in the semiconductor substrate. 12. The method of claim 1, wherein the implantation of the doping ions is performed such that at least one device doping region comprising a doping concentration which varies by less than 20% from a maximum doping concentration in the at least one device doping region is formed in the semiconductor substrate. 13. The method of claim 11, wherein the at least one device doping region has a vertical dimension of at least 500 nm. 14. The method of claim 1, wherein the implantation of the doping ions is performed so as to form a field stop region, a drift region, a channel stopper region or a body region of a vertical transistor arrangement or a vertical diode arrangement of the semiconductor device, or so as to form a cathode/anode region of a vertical diode arrangement, or a collector/emitter region or a source/drain region of a vertical transistor arrangement. 15. The method of claim 1, further comprising forming a device doping region comprising a graded doping profile by: forming a scattering oxide layer over at least part of a main implantation surface of the semiconductor substrate; andimplanting the doping ions into the semiconductor substrate through the scattering oxide layer such that deeper doping regions are formed in regions the semiconductor substrate without the scattering oxide layer than in regions of the semiconductor substrate covered by the scattering oxide layer. 16. The method of claim 1, wherein the implantation of the doping ions is performed so as to form a plurality of vertically extending compensation regions of a compensation device arrangement located adjacently to a plurality of vertically extending drift regions of the compensation device arrangement in the semiconductor substrate, and wherein the plurality of vertically extending compensation regions and the plurality of vertically extending drift regions of the compensation device arrangement are arranged alternatingly in the semiconductor substrate in a lateral direction. 17. The method of claim 1, wherein the implantation of the doping ions is performed so as to form a plurality of device doping regions adjacent to a back side of the semiconductor substrate, and wherein the plurality of device doping regions are laterally surrounded by a cathode/anode region of a vertical diode arrangement, or a source/drain or collector/emitter region of a vertical transistor arrangement. 18. The method of claim 1, wherein the doping ions comprise at least one doping ion type selected from the group consisting of: boron ions; phosphorus ions; aluminum ions; nitrogen ions; antimony ions; magnesium ions; indium ions; gallium ions; and arsenic ions. 19. The method of claim 1, wherein the upper target temperature limit is equal to the target temperature plus 30° C. 20. A method for forming a semiconductor device, the method comprising: implanting a predefined dose of doping ions into a semiconductor substrate with an implant energy of at least 100 keV, wherein a deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate; andcontrolling a temperature of the semiconductor substrate during the implantation of the predefined dose of doping ions so that the temperature of the semiconductor substrate is higher than 80° C. for more than 70% of an implant process time used for implanting the predefined dose of doping ions. 21. A method for forming a semiconductor device, the method comprising: forming a scattering oxide layer over at least part of a main implantation surface of a semiconductor substrate;implanting a predefined dose of doping ions into a semiconductor substrate through the scattering oxide layer such that deeper doping regions are formed in regions the semiconductor substrate without the scattering oxide layer than in regions of the semiconductor substrate covered by the scattering oxide layer; andcontrolling a temperature of the semiconductor substrate during the implantation of the predefined dose of doping ions so that the temperature of the semiconductor substrate is higher than 50° C. for more than 70% of an implant process time used for implanting the predefined dose of doping ions.
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